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ORCIDMitaro Namiki
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Publications
- 2017
[c49]Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura
, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki:
Building block multi-chip systems using inductive coupling through chip interface. ISOCC 2017: 152-154- 2016
- [j9]Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Trans. Electron. 99-C(8): 926-935 (2016) - 2015
- [j8]Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. IEICE Trans. Electron. 98-C(7): 559-568 (2015) - 2014
- [c46]Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. ASP-DAC 2014: 843-848 - [c44]Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura:
Design and evaluation of fine-grained power-gating for embedded microprocessors. DATE 2014: 1-6 - [c41]Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. ISSoC 2014: 1-7 - 2013
- [j7]Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki:
Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Trans. Electron. 96-C(4): 404-412 (2013) - [j6]Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33(6): 6-15 (2013) - [c37]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips 2013: 1-3 - [c36]Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL 2013: 1 - [c35]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium 2013: 1 - 2012
- [c31]Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546 - [c30]Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296 - [r1]Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, Masaaki Kondo, Mitaro Namiki, Hiroshi Nakamura:
Geyser. Handbook of Energy-Aware and Green Computing 2012: 49-65 - 2011
- [j3]Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano:
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. Inf. Media Technol. 6(4): 1092-1102 (2011) - [j2]Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano:
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. IPSJ Trans. Syst. LSI Des. Methodol. 4: 182-192 (2011) - [j1]Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo:
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31(6): 6-18 (2011) - [c25]Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo:
Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC 2011: 87-88 - [c24]Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo:
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. COOL Chips 2011: 1-3 - [c23]Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo:
Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT 2011: 1-8 - 2010
- [c20]Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo:
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC 2010: 369-370 - [c16]Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Adaptive power gating for function units in a microprocessor. ISQED 2010: 29-37 - 2009
- [c13]Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura:
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386 - 2008
- [c12]Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD 2008: 612-617
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