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2020 – today
- 2021
[c55]Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano:
M-KUBOS/PYNQ Cluster for multi-access edge computing. CANDAR 2021: 95-101
2010 – 2019
- 2019
- [j10]Atsushi Koshiba, Takahiro Hirofuchi, Ryousei Takano, Mitaro Namiki:
A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies. IEICE Trans. Inf. Syst. 102-D(12): 2377-2388 (2019) - [c54]Sayaka Terashima, Takuya Kojima
, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Mitaro Namiki:
A Preliminary Evaluation of Building Block Computing Systems. MCSoC 2019: 312-319 - [i2]Atsushi Koshiba, Takahiro Hirofuchi, Ryousei Takano, Mitaro Namiki:
A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies. CoRR abs/1908.02135 (2019) - 2018
- [c53]Atsushi Koshiba, Ying Yan, Zhongxin Guo, Mitaro Namiki, Lidong Zhou:
TEE-KV: Secure Immutable Key-Value Store for Trusted Execution Environments. SoCC 2018: 535 - [c52]Kazuhei Nagashima, Shinya Cho, Masayuki Horikoshi, Hiroki Manabe, Susumu Kanemune, Mitaro Namiki:
Design and development of bit arrow: a web-based programming learning environment. ICETC 2018: 85-91 - [c51]May Takada, Mitaro Namiki:
End-to-End Delay Model for Remote Surveillance over Internet and Mobile Networks. ISPACS 2018: 226-230 - [c50]Atsushi Koshiba, Ryuichi Sakamoto, Mitaro Namiki:
OpenCL Runtime for OS-Driven Task Pipelining on Heterogeneous Accelerators. RTCSA 2018: 236-237 - [i1]Shinsuke Hamada, Soramichi Akiyama, Mitaro Namiki:
Reactive NaN Repair for Applying Approximate Memory to Numerical Applications. CoRR abs/1804.00705 (2018) - 2017
- [c49]Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki:
Building block multi-chip systems using inductive coupling through chip interface. ISOCC 2017: 152-154 - [c48]Shinsuke Hamada, Atsushi Koshiba, Mitaro Namiki, Hideharu Amano:
Building block operating system for 3D stacked computer systems with inductive coupling interconnect. ISOCC 2017: 157-158 - [c47]Atsushi Koshiba, Takahiro Hirofuchi, Soramichi Akiyama, Ryousei Takano, Mitaro Namiki:
Towards write-back aware software emulator for non-volatile memory. NVMSA 2017: 1-6 - 2016
- [j9]Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Trans. Electron. 99-C(8): 926-935 (2016) - 2015
- [j8]Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. IEICE Trans. Electron. 98-C(7): 559-568 (2015) - 2014
- [c46]Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. ASP-DAC 2014: 843-848 - [c45]Motoki Wada, Mikiko Sato, Mitaro Namiki:
A fine grained power management supported by just-in-time compiler. COOL Chips 2014: 1-3 - [c44]Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura:
Design and evaluation of fine-grained power-gating for embedded microprocessors. DATE 2014: 1-6 - [c43]Mikiko Sato, Shigeyoshi Tsutsui, Noriyuki Fujimoto, Yuji Sato, Mitaro Namiki:
First results of performance comparisons on many-core processors in solving QAP with ACO: kepler GPU versus xeon PHI. GECCO (Companion) 2014: 1477-1478 - [c42]Hiroshi Miyata, Mitaro Namiki, Mikiko Sato:
pmqFlow: Design of propagation time measuring QoS system with OpenFlow for process automation. IECON 2014: 3693-3699 - [c41]Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. ISSoC 2014: 1-7 - [c40]Yuichi Tsujita, Kazumi Yoshinaga, Atsushi Hori, Mikiko Sato, Mitaro Namiki, Yutaka Ishikawa:
Multithreaded Two-Phase I/O: Improving Collective MPI-IO Performance on a Lustre File System. PDP 2014: 232-235 - [c39]Mikiko Sato, Go Fukazawa, Akio Shimada, Atsushi Hori, Yutaka Ishikawa, Mitaro Namiki:
Design of Multiple PVAS on InfiniBand Cluster System Consisting of Many-core and Multi-core. EuroMPI/ASIA 2014: 133 - 2013
- [j7]Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki:
Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Trans. Electron. 96-C(4): 404-412 (2013) - [j6]Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33(6): 6-15 (2013) - [c38]Tetsuro Honmura, Yuki Kondo, Tetsuya Yamada, Masashi Takada, Takumi Nitoh, Tohru Nojiri, Keisuke Toyama, Yasuhiko Saitoh, Hirofumi Nishi, Mikiko Sato, Mitaro Namiki:
Hardware support for resource partitioning in real-time embedded systems. COOL Chips 2013: 1-3 - [c37]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips 2013: 1-3 - [c36]Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL 2013: 1 - [c35]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium 2013: 1 - [c34]Hiroshi Miyata, Mitaro Namiki, Mikiko Sato:
sQoS: The design and prototyping of secure QoS for process automation system. IECON 2013: 5680-5685 - [c33]Kazumi Yoshinaga, Yuichi Tsujita, Atsushi Hori, Mikiko Sato, Mitaro Namiki, Yutaka Ishikawa:
A Delegation Mechanism on Many-Core Oriented Hybrid Parallel Computers for Scalability of Communicators and Communications in MPI. PDP 2013: 249-253 - [c32]Yuichi Tsujita, Kazumi Yoshinaga, Atsushi Hori, Mikiko Sato, Mitaro Namiki, Yutaka Ishikawa:
Improving Parallel I/O Performance Using Multithreaded Two-Phase I/O with Processor Affinity Management. PPAM (1) 2013: 714-723 - 2012
- [c31]Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546 - [c30]Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296 - [c29]Mikiko Sato, Go Fukazawa, Kiyohiko Nagamine, Ryuichi Sakamoto, Mitaro Namiki, Kazumi Yoshinaga, Yuichi Tsujita, Atsushi Hori, Yutaka Ishikawa:
A design of hybrid operating system for a parallel computer with multi-core and many-core processors. ROSS@ICS 2012: 9:1-9:8 - [c28]Kazumi Yoshinaga, Yuichi Tsujita, Atsushi Hori, Mikiko Sato, Mitaro Namiki, Yutaka Ishikawa:
Delegation-Based MPI Communications for a Hybrid Parallel Computer with Many-Core Architecture. EuroMPI 2012: 47-56 - [c27]Atsushi Hori, Toyohisa Kameyama, Yuichi Tsujita, Mitaro Namiki, Yutaka Ishikawa:
An Efficient Kernel-Level Blocking MPI Implementation. EuroMPI 2012: 153-162 - [c26]Ryuichi Sakamoto, Mikiko Sato, Yusuke Koizumi, Hideharu Amano, Mitaro Namiki:
An OpenCL Runtime Library for Embedded Multi-Core Accelerator. RTCSA 2012: 419-422 - [r1]Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, Masaaki Kondo, Mitaro Namiki, Hiroshi Nakamura:
Geyser. Handbook of Energy-Aware and Green Computing 2012: 49-65 - 2011
- [j5]Lei Zhao, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano:
A Leakage Efficient Data TLB Design for Embedded Processors. IEICE Trans. Inf. Syst. 94-D(1): 51-59 (2011) - [j4]Zhao Lei, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano:
A Leakage Efficient Instruction TLB Design for Embedded Processors. IEICE Trans. Inf. Syst. 94-D(8): 1565-1574 (2011) - [j3]Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano:
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. Inf. Media Technol. 6(4): 1092-1102 (2011) - [j2]Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano:
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. IPSJ Trans. Syst. LSI Des. Methodol. 4: 182-192 (2011) - [j1]Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo:
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31(6): 6-18 (2011) - [c25]Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo:
Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC 2011: 87-88 - [c24]Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo:
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. COOL Chips 2011: 1-3 - [c23]Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo:
Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT 2011: 1-8 - [c22]Mikiko Sato, Yuji Sato, Mitaro Namiki:
Acceleration experiment of genetic computations for sudoku solution on multi-core processors. GECCO (Companion) 2011: 823-824 - [c21]Hiroki Manabe, Susumu Kanemune, Mitaro Namiki, Yoshiaki Nakano:
CS Unplugged Assisted by Digital Materials for Handicapped People at Schools. ISSEP 2011: 82-93 - 2010
- [c20]Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo:
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC 2010: 369-370 - [c19]Mikiko Sato, Yuji Sato, Mitaro Namiki:
Proposal of a multi-core processor from the viewpoint of evolutionary computation. IEEE Congress on Evolutionary Computation 2010: 1-8 - [c18]Mikiko Sato, Yuji Sato, Mitaro Namiki:
Proposal of a multi-core processor architecture for effective evolutionary computation. GECCO 2010: 1321-1322 - [c17]Zhao Lei, Hui Xu, Daisuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki:
Reducing instruction TLB's leakage power consumption for embedded processors. Green Computing Conference 2010: 477-484 - [c16]Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Adaptive power gating for function units in a microprocessor. ISQED 2010: 29-37
2000 – 2009
- 2009
- [c15]Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara:
Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. ICPP 2009: 510-517 - [c14]Tomohiro Nishida, Susumu Kanemune, Yukio Idosaka, Mitaro Namiki, Tim Bell, Yasushi Kuno:
A CS unplugged design pattern. SIGCSE 2009: 231-235 - [c13]Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura:
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386 - 2008
- [c12]Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD 2008: 612-617 - 2007
- [c11]Jun Kanai, Mitaro Namiki, Kuniyasu Suzaki, Toshiki Yagi:
Mobile Thin-Client System with Fault Tolerance and Scalability by "HTTP-FUSE-KNOPPIX-BOX". PDPTA 2007: 207-213 - 2006
- [c10]Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki:
Implementation of PC Cluster System with Memory Mapped File by Commodity OS. PDPTA 2006: 902-908 - [c9]Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo:
A Model of Implementable SMT Processor on FPGA. PDPTA 2006: 909-915 - [c8]Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo:
Towards Reconfigurable Cache Memory for a Multithreaded Processor. PDPTA 2006: 916-924 - 2005
- [c7]Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo:
A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA 2005: 447-453 - [c6]Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki:
Development of a Thread Scheduler for SMT Processor Architecture. PDPTA 2005: 454-460 - 2004
- [c5]Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo:
Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA 2004: 317-323 - 2003
- [c4]Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki:
Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA 2003: 609-615 - [c3]Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki:
A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA 2003: 1669-1675 - [c2]Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki:
Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA 2003: 1775-1781
1990 – 1999
- 1991
- [c1]Toshio Souya, Eiichi Hayakawa, Masayuki Honma, Hidehiro Fukushima, Mitaro Namiki, Nobumasa Takahashi, Masaki Nakagawa:
Programming in a mother tongue: philosophy, implementation, practice and effect. COMPSAC 1991: 705-712
Coauthor Index
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