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ORCID16th COOL Chips 2013: Yokohama, Japan
- 2013 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVI, Yokohama, Japan, April 17-19, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-5780-7
- Kazuhisa Ishizaka, Takamichi Miyamoto, S. Akimoto, A. Iketani, T. Hosomi, Junji Sakai:
Power efficient realtime super resolution by virtual pipeline technique on a server with manycore coprocessors. 1-3 - Hidetomo Kobayashi, Kiyoshi Kato, Takuro Ohmaru, Seiichi Yoneda, Tatsuji Nishijima, Shuhei Maeda, Kazuaki Ohshima
, Hikaru Tamura, Hiroyuki Tomatsu, Tomoaki Atsumi, Yutaka Shionoiri, Yukio Maehashi, Jun Koyama, Shunpei Yamazaki:
Processor with 4.9-μs break-even time in power gating using crystalline In-Ga-Zn-oxide transistor. 1-3 - Dominic Hillenbrand, Akihiro Hayashi, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara:
Automatic parallelization, performance predictability and power control for mobile-applications. 1-3 - Junyoung Park, Injoon Hong, Gyeonghoon Kim, Youchang Kim, Kyuho Lee, Seongwook Park, Kyeongryeol Bong, Hoi-Jun Yoo:
A multi-granularity parallelism object recognition processor with content-aware fine-grained task scheduling. 1-3 - Tadao Nakamura:
Message from the Advisory Committee Chair. iii - Yoshio Masubuchi, Bert Gyselinckx, Michael McCool, Shintaro Momose, James Myers, Toshio Yoshida:
Panel discussions the next step in processor evolution. 1-2 - Hiroaki Kobayashi:
Message from the Organizing Committee Chair. i-ii - Makoto Ikeda, Fumio Arakawa:
Message from the Program Committee Chairs. iv-v - Sugako Otani, Naoshi Ishikawa, Hiroyuki Kondo:
RXv2 processor core for low-power microcontrollers. 1-3 - Tetsuro Honmura, Yuki Kondo, Tetsuya Yamada, Masashi Takada, Takumi Nitoh, Tohru Nojiri, Keisuke Toyama, Yasuhiko Saitoh, Hirofumi Nishi, Mikiko Sato, Mitaro Namiki:
Hardware support for resource partitioning in real-time embedded systems. 1-3 - Bert Gyselinckx, Hiroshi Kanayama, Michael McCool, Shintaro Momose, Takeshi Kataoka, James Myers, Toshio Yoshida:
Keynote & invited speaker's biography [7 biographies]. xxii-xxviii - Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
Architecture level TSV count minimization methodology for 3D tree-based FPGA. 1-3 - Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links. 1-3 - Masayuki Sato, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
A flexible insertion policy for dynamic cache resizing mechanisms. 1-3 - Yohei Kanehagi, Dan Umeda, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara:
Parallelization of automotive engine control software on embedded multi-core processor using OSCAR compiler. 1-3 - Wei Wang, Jun Yao, Youhui Zhang, Wei Xue, Yasuhiko Nakashima, Weimin Zheng:
HW/SW approaches to accelerate GRAPES in an FU array. 1-3 - Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. 1-3
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