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ORCIDCharvaka Duvvury
Person information
- affiliation: ESD Consultant, Plano, TX, USA
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Journal Articles
- 2015
[j8]Harald Gossner
, Charvaka Duvvury:
System efficient ESD design. Microelectron. Reliab. 55(12): 2607-2613 (2015)- 2006
- [j7]Charvaka Duvvury, Robert Steinhoff, Gianluca Boselli, Vijay Reddy, Hans Kunz, Steve Marum, Roger Cline:
Gate oxide failures due to anomalous stress from HBM ESD testers. Microelectron. Reliab. 46(5-6): 656-665 (2006) - 2005
- [j6]Gianluca Boselli, Charvaka Duvvury:
Trends and challenges to ESD and Latch-up designs for nanometer CMOS technologies. Microelectron. Reliab. 45(9-11): 1406-1414 (2005) - 2004
- [j5]Jorge Salcedo-Suñer, Charvaka Duvvury, Roger Cline, Alfonso Cadena-Hernandez:
Latchup in voltage tolerant circuits: a new phenomenon. Microelectron. Reliab. 44(4): 549-562 (2004) - 2002
- [j4]Craig Salling, Jerry Hu, Jeff Wu, Charvaka Duvvury, Roger Cline, Rith Pok:
Development of substrate-pumped nMOS protection for a 0.13 mum technology. Microelectron. Reliab. 42(6): 887-899 (2002) - 2001
- [j3]Steven H. Voldman, W. Anderson, R. Ashton, M. Chaine, Charvaka Duvvury, T. Maloney, E. Worley:
A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies. Microelectron. Reliab. 41(3): 335-348 (2001) - 1994
- [j2]Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury:
Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 482-493 (1994) - 1993
- [j1]Charvaka Duvvury, Ajith Amerasekera:
ESD: a pervasive reliability concern for IC technologies. Proc. IEEE 81(5): 690-702 (1993)
Conference and Workshop Papers
- 2006
- [c6]Christian Pacha, Klaus von Arnim, Thomas Schulz, Weize Xiong, Michael Gostkowski, Gerhard Knoblinger, Andrew Marshall, Thomas Nirschl, Jörg Berthold, Christian Russ, Harald Gossner, Charvaka Duvvury, Paul Patruno, C. Rinn Cleavelin, Klaus Schruefer:
Circuit design issues in multi-gate FET CMOS technologies. ISSCC 2006: 1656-1665 - 2002
- [c5]Charvaka Duvvury:
Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract). ISQED 2002: 8 - 2001
- [c4]Charvaka Duvvury:
ESD protection device issues for IC designs. CICC 2001: 41-48 - [c3]Charvaka Duvvury:
Issues in Deep Submicron State-of-the-Art ESD Design. ISQED 2001: 10 - 2000
- [c2]Charvaka Duvvury:
ESD: Design For IC Chip Quality and Reliability. ISQED 2000: 251- - 1993
- [c1]Carlos H. Díaz, Charvaka Duvvury, Sung-Mo Kang:
Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices. ISCAS 1993: 1389-1392
Coauthor Index
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