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2020 – today
- 2020
[c6]Chung-Cheng Chou, Zheng-Jun Lin, Chien-An Lai, Chin-I Su, Pei-Ling Tseng, Wei-Chi Chen, Wu-Chin Tsai, Wen-Ting Chu, Tong-Chern Ong, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang:
A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range. VLSI Circuits 2020: 1-2
2010 – 2019
- 2018
- [c5]Chien-An Lai, Chung-Cheng Chou, Chi-Hsiang Weng, Zheng-Jun Lin, Pei-Ling Tseng, Chien-Fan Wang, Chih-Chen Wang, Chin-I Su, Wei-Chi Chen, Yu-Cheng Lin, Tong-Chern Ong, Chi Chang, Yu-Der Chih, Tsung-Yung Jonathan Chang:
Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window. A-SSCC 2018: 13-16 - 2013
- [c4]Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Yu-Der Chih, Tong-Chern Ong, Tsung-Yung Jonathan Chang, Sreedhar Natarajan, Luan C. Tran:
Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology. ISSCC 2013: 224-225
2000 – 2009
- 2005
- [c3]Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Kuo-Feng Yu, Tong-Chern Ong:
A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O. ISCAS (2) 2005: 1198-1201 - 2003
- [j1]Carlos H. Diaz
, Mi-Chang Chang, Tong-Chern Ong, Jack Yuan-Chen Sun:
Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era. IEEE J. Solid State Circuits 38(3): 444-449 (2003) - 2002
- [c2]Jian-Hsing Lee, Yi-Hsun Wu, K. R. Peng, R. Y. Chang, Talee Yu, Tong-Chern Ong:
The embedded SCR NMOS and low capacitance ESD protection device. CICC 2002: 93-96 - [c1]Carlos H. Diaz, Mi-Chang Chang, Tong-Chern Ong, Jack Yuan-Chen Sun:
Application-dependent scaling tradeoffs and optimization in the SoC era. CICC 2002: 475-478
Coauthor Index
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