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Vivek Joshi
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Publications
- 2012
- [c12]Vivek Joshi, Kanak Agarwal, Dennis Sylvester:
Design-patterning co-optimization of SRAM robustness for double patterning lithography. ASP-DAC 2012: 713-718 - 2010
- [j2]Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal:
Mechanical Stress Aware Optimization for Leakage Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 722-736 (2010) - [c11]Vivek Joshi, Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Analyzing electrical effects of RTA-driven local anneal temperature variation. ASP-DAC 2010: 739-744 - [c10]Vivek Joshi, Michael Wieckowski, Gregory K. Chen, David T. Blaauw, Dennis Sylvester:
Analyzing the impact of Double Patterning Lithography on SRAM variability in 45nm CMOS. CICC 2010: 1-4 - [c9]Vivek Joshi, Valeriy Sukharev, Andres Torres, Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Closed-form modeling of layout-dependent mechanical stress. DAC 2010: 673-678 - [c8]Vivek Joshi, Kanak Agarwal, David T. Blaauw, Dennis Sylvester:
Analysis and optimization of SRAM robustness for double patterning lithography. ICCAD 2010: 25-31 - [c7]Vivek Joshi, Kanak Agarwal, Dennis Sylvester:
Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices. ISQED 2010: 158-162 - 2009
- [j1]Rajeev R. Rao, Vivek Joshi, David T. Blaauw, Dennis Sylvester:
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic. ACM Trans. Design Autom. Electr. Syst. 15(1): 5:1-5:27 (2009) - 2008
- [c5]Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal:
Leakage power reduction using stress-enhanced layouts. DAC 2008: 912-917 - [c4]Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw:
STEEL: a technique for stress-enhanced standard cell library design. ICCAD 2008: 691-697 - [c3]Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal:
Stress aware layout optimization. ISPD 2008: 168-174 - 2007
- [c2]Vivek Joshi, David T. Blaauw, Dennis Sylvester:
Soft-edge flip-flops for improved timing yield: design and optimization. ICCAD 2007: 667-673 - 2006
- [c1]Vivek Joshi, Rajeev R. Rao, David T. Blaauw, Dennis Sylvester:
Logic SER Reduction through Flipflop Redesign. ISQED 2006: 611-616
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