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Siddhartha Nath
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Publications
- 2017
- [j5]Prabhav Agrawal, Mike Broxterman, Biswadeep Chatterjee, Patrick Cuevas, Kathy H. Hayashi, Andrew B. Kahng, Pranay K. Myana, Siddhartha Nath:
Optimal Scheduling and Allocation for IC Design Management and Cost Reduction. ACM Trans. Design Autom. Electr. Syst. 22(4): 60:1-60:30 (2017) - 2016
- [c19]Wei-Ting Jonas Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath:
Learning-based prediction of embedded memory timing failures during initial floorplan design. ASP-DAC 2016: 178-185 - [c18]Wei-Ting Jonas Chan, Yang Du, Andrew B. Kahng, Siddhartha Nath, Kambiz Samadi:
BEOL stack-aware routability prediction from placement using data mining techniques. ICCD 2016: 41-48 - 2015
- [j4]Andrew B. Kahng, Bill Lin, Siddhartha Nath:
ORION3.0: A Comprehensive NoC Router Estimation Tool. IEEE Embed. Syst. Lett. 7(2): 41-45 (2015) - [j3]Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath, Bongil Park:
Optimization of Overdrive Signoff in High-Performance and Low-Power ICs. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1552-1556 (2015) - [c17]Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee:
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. DAC 2015: 26:1-26:6 - [c16]Wei-Ting Jonas Chan, Siddhartha Nath, Andrew B. Kahng, Yang Du, Kambiz Samadi:
3DIC benefit estimation and implementation guidance from 2DIC implementation. DAC 2015: 30:1-30:6 - [c15]Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins:
Toward Metrics of Design Automation Research Impact. ICCAD 2015: 263-270 - [c14]Andrew B. Kahng, Mulong Luo, Siddhartha Nath:
SI for free: machine learning of interconnect coupling delay and transition effects. SLIP 2015: 1-8 - 2014
- [c13]Seung-Soo Han, Andrew B. Kahng, Siddhartha Nath, Ashok S. Vydyanathan:
A deep learning methodology to proliferate golden signoff timing. DATE 2014: 1-6 - [c12]Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee, Siddhartha Nath:
OCV-aware top-level clock tree optimization. ACM Great Lakes Symposium on VLSI 2014: 33-38 - [c11]Juan Antonio Carballo, Wei-Ting Jonas Chan, Paolo A. Gargini, Andrew B. Kahng, Siddhartha Nath:
ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap. ICCD 2014: 139-146 - [c10]Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath, Ichiro Yamamoto:
The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap. ICCD 2014: 153-160 - [c9]Andrew B. Kahng, Siddhartha Nath:
Optimal reliability-constrained overdrive frequency selection in multicore systems. ISQED 2014: 300-308 - [c8]Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath:
Methodology for electromigration signoff in the presence of adaptive voltage scaling. SLIP 2014: 6:1-6:7 - 2013
- [c7]Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath:
Optimization of overdrive signoff. ASP-DAC 2013: 344-349 - [c6]Andrew B. Kahng, Siddhartha Nath, Tajana Rosing:
On potential design impacts of electromigration awareness. ASP-DAC 2013: 527-532 - [c5]Andrew B. Kahng, Bill Lin, Siddhartha Nath:
Enhanced metamodeling techniques for high-dimensional IC design estimation problems. DATE 2013: 1861-1866 - [c4]Andrew B. Kahng, Ilgweon Kang, Siddhartha Nath:
Incremental multiple-scan chain ordering for ECO flip-flop insertion. ICCAD 2013: 705-712 - [c3]Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, Jyoti Wadhwani:
Learning-based approximation of interconnect delay and slew in signoff timing tools. SLIP 2013: 1-8 - [c2]Andrew B. Kahng, Bill Lin, Siddhartha Nath:
High-dimensional metamodeling for prediction of clock tree synthesis outcomes. SLIP 2013: 1-7 - 2012
- [c1]Andrew B. Kahng, Bill Lin, Siddhartha Nath:
Explicit modeling of control and data for improved NoC router estimation. DAC 2012: 392-397
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