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ORCIDYinghua Min
- > Home > Persons > Yinghua Min
Publications
- 2005
[j21]Jie Wu, Feng Gao, Zhongcheng Li, Yinghua Min:
Optimal, and reliable communication in hypercubes using extended safety vectors. IEEE Trans. Reliab. 54(3): 402-411 (2005)- 2002
- [j15]Huawei Li, Yinghua Min, Zhongcheng Li:
Clustering of behavioral phases in FSMs and its applications to VLSI test. Sci. China Ser. F Inf. Sci. 45(6): 462-478 (2002) - 2001
- [c22]Huawei Li, Yinghua Min, Zhongcheng Li:
An RT-Level ATPG Based on Clustering of Circuit States. Asian Test Symposium 2001: 213-218 - 2000
- [j12]Huawei Li
, Zhongcheng Li, Yinghua Min:
Reduction of Number of Paths to be Tested in Delay Testing. J. Electron. Test. 16(5): 477-485 (2000) - [c17]Jie Wu, Feng Gao, Zhongcheng Li, Yinghua Min:
Optimal Fault-Tolerant Routing in Hypercubes Using Extended Safety Vectors. ICPADS 2000: 264-271 - 1999
- [j11]Yinghua Min, Zhongcheng Li:
An analytical delay model. J. Comput. Sci. Technol. 14(2): 97-115 (1999) - 1998
- [j10]Yinghua Min, Zhongcheng Li:
IDDT Testing versus IDDQ Testing. J. Electron. Test. 13(1): 51-55 (1998) - [c15]Zhongcheng Li, Yinghua Min, Robert K. Brayton:
A New Low-Cost Method for Identifying Untestable Path Delay Faults. Asian Test Symposium 1998: 76-81 - [c14]Huawei Li, Zhongcheng Li, Yinghua Min:
Delay Testing with Double Observations. Asian Test Symposium 1998: 96- - 1997
- [j8]Zhuxing Zhao, Yinghua Min, Zhongcheng Li:
Path sensitization. J. Comput. Sci. Technol. 12(3): 271-282 (1997) - [c13]Wangning Long, Shiyuan Yang, Zhongcheng Li, Yinghua Min:
Memory Efficient ATPG for Path Delay Faults. Asian Test Symposium 1997: 326-331 - [c11]Yinghua Min, Zhuxing Zhao, Zhongcheng Li:
IDDT Testing. Asian Test Symposium 1997: 378-383 - [c10]Zhongcheng Li, Yuhong Zhao, Yinghua Min, Robert K. Brayton:
Timed Binary Decision Diagrams. ICCD 1997: 352-357 - [c9]Zhongcheng Li, Robert K. Brayton, Yinghua Min:
Efficient Identification of Non-Robustly Untestable Path Delay Faults. ITC 1997: 992-997 - 1996
- [c8]Zhuxing Zhao, Zhongcheng Li, Yinghua Min:
Waveform Polynomial Manipulation Using Bdds. Asian Test Symposium 1996: 136-141 - [c7]Yinghua Min, Zhuxing Zhao, Zhongcheng Li:
An Analytical Delay Model Based on Boolean Process. VLSI Design 1996: 162-165 - 1995
- [c6]Yinghua Min, Zhuxing Zhao, Zhongcheng Li:
Boolean process-an analytical approach to circuit representation (II). Asian Test Symposium 1995: 26-32 - 1994
- [c3]Yinghua Min, Yutang Zhou, Zhongcheng Li, Cheng Ye, Yuqi Pan:
Behavioral Design and Prototyping of a Fail-Safe System. VLSI Design 1994: 159-162 - 1993
- [c2]Yinghua Min, Zhongcheng Li:
Evaluation of test generation algorithms. VTS 1993: 348-350 - 1986
- [j1]Yinghua Min, Zhongcheng Li:
Pseudo-Exhaustive Testing Strategy for Large Combinational Circuits. Comput. Syst. Sci. Eng. 1(4): 213-220 (1986)
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