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ORCIDShekhar Borkar
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Publications
- 2014
[c71]Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar:
Resiliency for many-core system on a chip. ASP-DAC 2014: 388-389- 2013
- [c68]Tanay Karnik, Mondira (Mandy) Deb Pant, Shekhar Borkar:
Power management and delivery for high-performance microprocessors. DAC 2013: 159:1-159:3 - 2011
- [j36]Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar:
Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. IET Comput. Digit. Tech. 5(3): 205-212 (2011) - [c56]Donald S. Gardner, Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Shekhar Borkar:
Integrated inductors with magnetic materials for on-chip power conversion. Hot Chips Symposium 2011: 1-36 - [c55]Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar:
3DICs for tera-scale computing: a case study. ISPD 2011: 77-78 - 2009
- [j30]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah
, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi:
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits 44(1): 174-185 (2009) - [c48]Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar:
Circuit techniques for dynamic variation tolerance. DAC 2009: 4-7 - 2008
- [c43]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi:
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC 2008: 274-275 - 2005
- [j20]Peter Hazucha, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Paul Hack, Gregory E. Dermer, Siva G. Narendra, Donald S. Gardner, Tanay Karnik, Vivek De, Shekhar Borkar:
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. IEEE J. Solid State Circuits 40(4): 838-845 (2005) - [j19]Peter Hazucha, Tanay Karnik, Bradley A. Bloechel, Colleen Parsons, David Finan, Shekhar Borkar:
Area-efficient linear regulator with ultra-fast load regulation. IEEE J. Solid State Circuits 40(4): 933-940 (2005) - 2004
- [j16]Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar:
Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. IEEE J. Solid State Circuits 39(9): 1536-1543 (2004) - [c29]Shekhar Borkar, Tanay Karnik, Vivek De:
Design and reliability challenges in nanometer technologies. DAC 2004: 75 - 2003
- [c24]Shekhar Borkar, Tanay Karnik, Siva G. Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De:
Parameter variations and impact on circuits and microarchitecture. DAC 2003: 338-342 - 2002
- [c15]Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar:
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC 2002: 486-491 - [c14]Tanay Karnik, Shekhar Borkar, Vivek De:
Sub-90nm technologies: challenges and opportunities for CAD. ICCAD 2002: 203-206
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