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ORCID23rd Hot Chips Symposium 2011: Stanford, CA, USA
- 2011 IEEE Hot Chips 23 Symposium (HCS), Stanford, CA, USA, August 17-19, 2011. IEEE 2011, ISBN 978-1-4673-8877-1
- Mike Galles, Shrijeet Mukherjee:
Sereno: A second generation virtualized network interface controller. 1-19 - Ruud A. Haring:
The Blue Gene/Q Compute chip. 1-20 - Simon Segars:
ARM processor evolution: Bringing high performance to mobile devices. 1-37 - Harry Li:
Facebook: Server board design. 1-20 - Juan A. Colmenares, Sarah Bird, Gage Eads, Steven A. Hofmeyr, Albert Kim, Rohit Poddar, Hilfi Alkaff, Krste Asanovic, John Kubiatowicz:
Tessellation operating system: Building a real-time, responsive, high-throughput client OS for many-core architectures. 1 - R. Curtis Harting, Vishal Parikh, William J. Dally:
The utility of fast active messages on many-core chips: Efficient supercomputing project. 1 - Chris Rowen, Dan Nicolaescu, Rajiv Ravindran, David Heine, Grant Martin, James Kim, Dror E. Maydan, Nupur Andrews, Bill Huffman, Vakis Papaparaskeva, Shay Gal-On, Peter R. Nuth, Pushkar Patwardhan, Manish Paradkar:
The world's fastest DSP core: Breaking the 100 GMAC/s barrier. 1-25 - Oded Lempel:
2nd Generation Intel® Core Processor Family: Intel® Core i7, i5 and i3. 1-48 - Elad Alon, Hanh-Phuc Le
, Seth Sanders:
Fully integrated switched-capacitor DC-DC conversion. 1-30 - Mike Davies:
One billion packet per second frame processing pipeline. 1-24 - Michael J. Miller:
Bandwidth engine® serial memory chip breaks 2 billion accesses/sec. 1-23 - Daniel Sánchez, Christos Kozyrakis:
A few ways can take you a long way: Efficient and highly associative caches with scalable partitioning for many-core CMPs. 1 - Aaron Severance, Guy Lemieux:
VENICE: A compact vector processor for FPGA applications. 1-5 - Steve Cousins:
Challenges of building personal robots. 1-36 - Ashutosh Dhodapkar, Gary Lauterbach, Sean Lie, Dhiraj Mallick, Jim Bauman, Sundar Kanthadai, Toru Kuzuhara, Gene Shen, Min Xu, Chris Zhang:
SeaMicro SM10000-64 server: Building datacenter servers using cell phone chips. 1-18 - George Cox, Charles Dike, D. J. Johnston:
Intel's digital random number generator (DRNG). 1-13 - J. Thomas Pawlowski:
Hybrid memory cube (HMC). 1-24 - David May:
XMOS architecture XS1 chips. 1-30 - Vidya Rajagopalan, Vamsi Boppana, Sandeep Dutta, Brad Taylor, Ralph Wittig:
Xilinx Zynq-7000 EPP: An extensible processing platform family. 1-24 - Carl Ramey:
TILE-Gx100 ManyCore processor: Acceleration interfaces and architecture. 1-21 - Amir Michael:
Facebook: The open compute project. 1-41 - Stephen Kosonocky:
Practical power gating and dynamic voltage/frequency scaling. 1-62 - Denis Foley, Maurice Steinman, Alexander Branover, Greg Smaus, Antonio Asaro, Swamy Punyamurtula, Ljubisa Bajic:
AMD'S "LLANO" Fusion APU. 1-38 - Steven R. Undy:
Poulson: An 8 core 32 nm next generation Intel® Itanium® processor. 1-22 - Sean White:
High-performance power-efficient x86-64 server and desktop processors using the core codenamed "Bulldozer". 1-32 - Dongrui Fan, Hao Zhang, Da Wang, Xiaochun Ye, Fenglong Song, Junchao Zhang, Lingjun Fan:
High-efficient architecture of Godson-T many-core processor. 1-31 - Donald S. Gardner, Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Shekhar Borkar:
Integrated inductors with magnetic materials for on-chip power conversion. 1-36 - Pierluigi Sarti:
Facebook: Efficient power distribution: 277Vac distribution w/o centralized UPS 95% high efficiency solution battery cabinet as distributed backup energy unit. 1-33 - Dawson Yee, Scott McEldowney:
Electrons, photons, phonons, wave, bits, and industrial design: Microsoft kinect sensor: Hot chips 23. 1-20 - Jim Demmel:
Rethinking algorithms for future architectures: Communication-avoiding algorithms. 1-63 - Mochamad Asri:
Efficient fetch mechanism by employing instruction register. 1-5 - Efi Rotem, Alon Naveh, Doron Rajwan, Avinash Ananthakrishnan, Eliezer Weissmann:
Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy Bridge. 1-33 - David Moloney:
1TOPS/W software programmable media processor. 1-24 - Jeff Pangborn:
Building a 40 Gbps next generation virtualized security processor: HOT CHIPS 23 - August 2011. 1-21 - Robert T. Golla, Paul J. Jordan:
T4: A highly threaded server-on-a-chip with native support for heterogeneous computing. 1-21 - Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic:
The Maven vector-thread architecture. 1 - Ramin Shirani, Ramin Farjadrad:
Low-power high-density 10GBASE-T ethernet transceiver. 1-20 - Richard E. Kessler:
The Cavium 32 Core OCTEON II 68xx. 1-33 - Hong Jiang:
The Intel® Quick Sync Video technology in the 2nd-generation Intel Core processor family. 1-23
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