"Pareto Points in SRAM Design Using the Sleepy Stack Approach."

Jun-Cheol Park, Vincent John Mooney III (2005)

> Home

Details and statistics

DOI: 10.1007/978-0-387-73661-7_11

access: open

type: Conference or Workshop Paper

metadata version: 2018-06-26

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - conf/vlsi/ParkM05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/ParkM05
Jun-Cheol Park, Vincent John Mooney III:
Pareto Points in SRAM Design Using the Sleepy Stack Approach. VLSI-SoC 2005: 163-177

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.