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Publication search results
found 31 matches
- 1995
- S. Q. Zheng, Bin Cong, Saïd Bettayeb:
Trade-Off Considerations in Designing Efficient VLSI Feasible Interconnection Networks. VLSI Design 2(4): 365-374 (1995) - Sajal K. Das, Sabine R. Öhring, Amit K. Banerjee:
Embeddings into Hyper Petersen Networks: Yet Another Hypercube-Like Interconnection Topology. VLSI Design 2(4): 335-351 (1995) - Kazuhiro Aoyama, Andrew A. Chien:
The Cost of Adaptivity and Virtual Lanes in a Wormhole Router. VLSI Design 2(4): 315-333 (1995) - Susan R. Dickey, Richard Kenner:
Design of Components for a Low Cost Combining Switch. VLSI Design 2(4): 287-303 (1995) - Ke Qiu, Selim G. Akl:
On Some Properties of the Star Graph. VLSI Design 2(4): 389-396 (1995) - M. T. Raghunath, Abhiram Ranade:
Designing Interconnection Networks for Multi-level Packaging. VLSI Design 2(4): 375-388 (1995) - Isaac D. Scherson, Chi-Kai Chien:
Least Common Ancestor Networks. VLSI Design 2(4): 353-364 (1995) - Pradip K. Srimani:
Guest Editor's Introduction. VLSI Design 2(4): i-ii (1995) - Peter W. Thompson, Julian D. Lewis:
The STC104 Packet Routing Chip. VLSI Design 2(4): 305-314 (1995) - 1994
- Yang Cai, D. F. Wong, Jason Cong:
Channel Density Minimization by Pin Permutation. VLSI Design 2(2): 171-183 (1994) - Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh:
On the Minimum Density Interconnection Tree Problem. VLSI Design 2(2): 157-169 (1994) - Peter J. Ashenden, Henry Detmold, Wayne S. McKeen:
Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms. VLSI Design 2(1): 1-16 (1994) - Fadi Busaba, Parag K. Lala:
Techniques for Self-Checking Combinational Logic Synthesis. VLSI Design 2(3): 209-221 (1994) - Chien-In Henry Chen:
Partitioning Techniques for Built-In Self-Test Design. VLSI Design 2(3): 185-198 (1994) - Cheng-Hsi Chen, Ioannis G. Tollis:
Area Optimization of Slicing Floorplans in Parallel. VLSI Design 2(2): 143-156 (1994) - Hassan Farhat, Steven G. From:
A Quadratic Programming Approach to Estimating the Testability and Random or Deterministic Coverage of a VLSl Circuit. VLSI Design 2(3): 223-231 (1994) - Anand V. Hudli, Raghu V. Hudli:
Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits. VLSI Design 2(1): 69-80 (1994) - Ali R. Hurson, Simin H. Pakzad:
Modular Scheme for Designing Special Purpose Associative Memories and Beyond. VLSI Design 2(3): 267-286 (1994) - Hyung Ki Lee, Dong S. Ha:
An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits. VLSI Design 2(3): 199-207 (1994) - Ausif Mahmood, Jayantha Herath, J. Jayasumana:
An Improved Data Flow Architecture for Logic Simulation Acceleration. VLSI Design 2(3): 259-265 (1994) - Rafic Z. Makki, Shyang-Tai Su:
Analysis and Characterization of State Assignment Techniques for Sequential Machines. VLSI Design 2(1): 81-88 (1994) - Chi-Yu Mao, Yu Hen Hu:
SEGMA: A Simulated Evolution Gate-Matrix Layout Algorithm. VLSI Design 2(3): 241-257 (1994) - Subbu Muddappa, Rafic Z. Makki, Zbigniew Michalewicz, Sridhar Isukapalli:
Pioneer: A New Tool for Coding of Multi-Level Finite State Machines Based on Evolution Programming. VLSI Design 2(2): 105-116 (1994) - Nohbyung Park, Fadi J. Kurdahi:
Register-Transfer Synthesis of Pipelined Data Paths. VLSI Design 2(1): 17-32 (1994) - C. P. Ravikumar, Haroon Rasheed:
TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing. VLSI Design 2(3): 233-239 (1994) - Youssef Saab, Cheng-Hua Chen:
An Effective Solution to the Linear Placement Problem. VLSI Design 2(2): 117-129 (1994) - Andrzej Sobski, Alexander Albicki:
High Throughput Error Control Using Parallel CRC. VLSI Design 2(1): 33-50 (1994) - Spyros Tragoudas:
On Channel Routing Problems With Interchangeable Terminals. VLSI Design 2(1): 51-68 (1994) - Kuo-Hua Wang, Cheng Chen, Ting Ting Hwang:
Technology Mapping for FPGA Using Generalized Functional Decomposition. VLSI Design 2(2): 89-103 (1994) - Si-Qing Zheng, Dian Zhou:
Preface. VLSI Design 2(2): i (1994)
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