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ORCID"An Improved Data Flow Architecture for Logic Simulation Acceleration."
Ausif Mahmood, Jayantha Herath, J. Jayasumana (1994)
- Ausif Mahmood, Jayantha Herath, J. Jayasumana:
An Improved Data Flow Architecture for Logic Simulation Acceleration. VLSI Design 2(3): 259-265 (1994)
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