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Publication search results
found 25 matches
- 2005
- Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler:
Post-Verification Debugging of Hierarchical Designs. MTV 2005: 42-47 - Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. MTV 2005: 55-62 - Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero:
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets. MTV 2005: 37-41 - David Berner, Hiren D. Patel, Deepak Mathaikutty, Sandeep K. Shukla:
Automated Extraction of Structural Information from SystemC-based IP for Validation. MTV 2005: 99-104 - Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova:
Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. MTV 2005: 111-118 - Nicola Bombieri, Andrea Fedeli, Franco Fummi:
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling. MTV 2005: 127-132 - Jorge Campos, Hussain Al-Asaad:
Search-Space Optimizations for High-Level ATPG. MTV 2005: 84-89 - Jennifer Dworak:
An Investigation of Excitation Balance and Additional Mandatory Conditions for the Diagnosis of Fortuitously Detected Defects. MTV 2005: 48-54 - Daniel Große, Ulrich Kühne, Rolf Drechsler:
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. MTV 2005: 133-137 - Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli:
A Pseudo-Deterministic Functional ATPG based on EFSM Traversing. MTV 2005: 70-75 - Marc Herbstritt, Bernd Becker:
On SAT-based Bounded Invariant Checking of Blackbox Designs. MTV 2005: 23-28 - Brian Kahne, Magdy S. Abadir:
Retiming Verification Using Sequential Equivalence Checking. MTV 2005: 138-142 - Brian Kahne, Aseem Gupta, Peter Wilson, Nikil D. Dutt:
An Introduction to the Plasma Language. MTV 2005: 12-22 - Soohong P. Kim:
Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors. MTV 2005: 105-110 - Prabhat Mishra, Heon-Mo Koo, Zhuo Huang:
Language-driven Validation of Pipelined Processors using Satisfiability Solvers. MTV 2005: 119-126 - John Mark Nolen, Rabi N. Mahapatra:
A TDM Test Scheduling Method for Network-on-Chip Systems. MTV 2005: 90-98 - Wei Qin, Sharad Malik:
A Study of Architecture Description Languages from a Model-based Perspective. MTV 2005: 3-11 - Tobias Schubert, Matthew D. T. Lewis, Bernd Becker:
PaMira - A Parallel SAT Solver with Knowledge Sharing. MTV 2005: 29-36 - Charles H.-P. Wen, Li-C. Wang:
Simulation Data Mining for Functional Test Pattern Justification. MTV 2005: 76-83 - Preface. MTV 2005
- Acknowledgement. MTV 2005
- Workshop Organizing Committee. MTV 2005
- Program Committee. MTV 2005
- Bin Xue, D. M. H. Walker:
Is IDDQ Test of Microprocessors Feasible? MTV 2005: 63-69 - Magdy S. Abadir, Li-C. Wang:
Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA. IEEE Computer Society 2005, ISBN 0-7695-2627-6 [contents]
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