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Publication search results
found 26 matches
- 2010
- Wolfgang Müller, Marcio F. da S. Oliveira, Henning Zabel, Markus Becker:
Verification of real-time properties for Hardware-dependent Software. HLDVT 2010: 154-159 - Samar Abdi:
Automatic generation of host-compiled timed TLMs for high level design. HLDVT 2010: 103-104 - Sumit Ahuja, Wei Zhang, Sandeep K. Shukla:
System level simulation guided approach to improve the efficacy of clock-gating. HLDVT 2010: 9-16 - Pranav Ashar:
Clock domain verification challenges and scalable solutions. HLDVT 2010: 66 - Rajiv Bhatia, Eyal Bin, Eitan Marcus, Gil Shurek:
An ontology and constraint based approach to cache preloading. HLDVT 2010: 129-136 - Nicola Bombieri, Franco Fummi, Valerio Guarnieri:
Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs. HLDVT 2010: 105-112 - Nicola Bombieri, Giuseppe Di Guglielmo, Luigi Di Guglielmo, Michele Ferrari, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Alessandro Venturelli:
HIFSuite: Tools for HDL code conversion and manipulation. HLDVT 2010: 40-41 - Maurizio Caramia, Michele Fabiano, Andrea Miele, Roberto Piazza, Paolo Prinetto:
Automated synthesis of EDACs for FLASH memories with user-selectable correction capability. HLDVT 2010: 113-120 - Satrajit Chatterjee, Michael Kishinevsky, Ümit Y. Ogras:
Quick formal modeling of communication fabrics to enable verification. HLDVT 2010: 42-49 - Weiwei Chen, Xu Han, Rainer Dömer:
ESL design and multi-core validation using the System-on-Chip Environment. HLDVT 2010: 142-147 - Nicholas Donataccio, Hao Zheng:
An improvement in decomposed reachability analysis for symbolic model checking. HLDVT 2010: 50-57 - Ashvin Dsouza:
Static analysis of deadends in SVA constraints. HLDVT 2010: 82-89 - Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten:
Model reduction techniques for the formal verification of hardware dependent software. HLDVT 2010: 148-153 - Rainer Findenig, Thomas Leitner, Michael Velten, Wolfgang Ecker:
Fast and accurate UML State Chart modeling using TLM+ control flow abstraction. HLDVT 2010: 97-102 - Ming Gao, Kwang-Ting Cheng:
A case study of Time-Multiplexed Assertion Checking for post-silicon debugging. HLDVT 2010: 90-96 - Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon:
Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams. HLDVT 2010: 33-39 - Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Stefano Soffia, Marco Roveri:
Semi-formal functional verification by EFSM traversing via NuSMV. HLDVT 2010: 58-65 - Hoang Minh Le, Daniel Große, Rolf Drechsler:
Towards analyzing functional coverage in SystemC TLM property checking. HLDVT 2010: 67-74 - Yogesh S. Mahajan, Sharad Malik:
Utility of transaction-level hardware models in refinement checking. HLDVT 2010: 121-128 - Rishiyur S. Nikhil:
ESL flows are enabled by high-level synthesis with universality. HLDVT 2010: 137 - John Sanguinetti, Eugene Zhang:
The relationship of code coverage metrics on high-level and RTL code. HLDVT 2010: 138-141 - Omid Sarbishei, Yu Pang, Katarzyna Radecka:
Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks. HLDVT 2010: 25-32 - Alper Sen, Magdy S. Abadir:
Coverage metrics for verification of concurrent SystemC designs using mutation testing. HLDVT 2010: 75-81 - Bart Vermeulen, Kees Goossens:
Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks. HLDVT 2010: 1-8 - Haiqiong Yao, Hao Zheng, Chris J. Myers:
State space reductions for scalable verification of asynchronous designs. HLDVT 2010: 17-24 - IEEE International High Level Design Validation and Test Workshop, HLDVT 2010, Anaheim, CA, USA, 10-12 June 2010. IEEE Computer Society 2010, ISBN 978-1-4244-7805-7 [contents]
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retrieved on 2024-04-28 02:07 CEST from data curated by the dblp team
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