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export results for "toc:db/conf/hldvt/hldvt2010.bht:"
download as .bib file
@inproceedings{DBLP:conf/hldvt/0003OZB10,
author = {Wolfgang M{\"{u}}ller and
Marcio F. da S. Oliveira and
Henning Zabel and
Markus Becker},
title = {Verification of real-time properties for Hardware-dependent Software},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {154--159},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496644},
doi = {10.1109/HLDVT.2010.5496644},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/0003OZB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/Abdi10,
author = {Samar Abdi},
title = {Automatic generation of host-compiled timed TLMs for high level design},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {103--104},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496655},
doi = {10.1109/HLDVT.2010.5496655},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/Abdi10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/AhujaZS10,
author = {Sumit Ahuja and
Wei Zhang and
Sandeep K. Shukla},
title = {System level simulation guided approach to improve the efficacy of
clock-gating},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {9--16},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496669},
doi = {10.1109/HLDVT.2010.5496669},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/AhujaZS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/Ashar10,
author = {Pranav Ashar},
title = {Clock domain verification challenges and scalable solutions},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {66},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496661},
doi = {10.1109/HLDVT.2010.5496661},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/Ashar10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/BhatiaBMS10,
author = {Rajiv Bhatia and
Eyal Bin and
Eitan Marcus and
Gil Shurek},
title = {An ontology and constraint based approach to cache preloading},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {129--136},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496651},
doi = {10.1109/HLDVT.2010.5496651},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/BhatiaBMS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/BombieriFG10,
author = {Nicola Bombieri and
Franco Fummi and
Valerio Guarnieri},
title = {Automatic synthesis of {OSCI} {TLM-2.0} models into {RTL} bus-based
IPs},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {105--112},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496652},
doi = {10.1109/HLDVT.2010.5496652},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/BombieriFG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/BombieriGGFFPSV10,
author = {Nicola Bombieri and
Giuseppe Di Guglielmo and
Luigi Di Guglielmo and
Michele Ferrari and
Franco Fummi and
Graziano Pravadelli and
Francesco Stefanni and
Alessandro Venturelli},
title = {HIFSuite: Tools for {HDL} code conversion and manipulation},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {40--41},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496665},
doi = {10.1109/HLDVT.2010.5496665},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/BombieriGGFFPSV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/CaramiaFMPP10,
author = {Maurizio Caramia and
Michele Fabiano and
Andrea Miele and
Roberto Piazza and
Paolo Prinetto},
title = {Automated synthesis of EDACs for {FLASH} memories with user-selectable
correction capability},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {113--120},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496653},
doi = {10.1109/HLDVT.2010.5496653},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/CaramiaFMPP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/ChatterjeeKO10,
author = {Satrajit Chatterjee and
Michael Kishinevsky and
{\"{U}}mit Y. Ogras},
title = {Quick formal modeling of communication fabrics to enable verification},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {42--49},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496662},
doi = {10.1109/HLDVT.2010.5496662},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/ChatterjeeKO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/ChenHD10,
author = {Weiwei Chen and
Xu Han and
Rainer D{\"{o}}mer},
title = {{ESL} design and multi-core validation using the System-on-Chip Environment},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {142--147},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496646},
doi = {10.1109/HLDVT.2010.5496646},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/ChenHD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/DonataccioZ10,
author = {Nicholas Donataccio and
Hao Zheng},
title = {An improvement in decomposed reachability analysis for symbolic model
checking},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {50--57},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496663},
doi = {10.1109/HLDVT.2010.5496663},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/DonataccioZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/Dsouza10,
author = {Ashvin Dsouza},
title = {Static analysis of deadends in {SVA} constraints},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {82--89},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496656},
doi = {10.1109/HLDVT.2010.5496656},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/Dsouza10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/EckerEFSV10,
author = {Wolfgang Ecker and
Volkan Esen and
Rainer Findenig and
Thomas Steininger and
Michael Velten},
title = {Model reduction techniques for the formal verification of hardware
dependent software},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {148--153},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496647},
doi = {10.1109/HLDVT.2010.5496647},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/EckerEFSV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/FindenigLVE10,
author = {Rainer Findenig and
Thomas Leitner and
Michael Velten and
Wolfgang Ecker},
title = {Fast and accurate {UML} State Chart modeling using TLM\({}^{\mbox{+}}\)
control flow abstraction},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {97--102},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496654},
doi = {10.1109/HLDVT.2010.5496654},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/FindenigLVE10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/GaoC10,
author = {Ming Gao and
Kwang{-}Ting Cheng},
title = {A case study of Time-Multiplexed Assertion Checking for post-silicon
debugging},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {90--96},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496657},
doi = {10.1109/HLDVT.2010.5496657},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/GaoC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/Gomez-PradoKCB10,
author = {Daniel Gomez{-}Prado and
Dusung Kim and
Maciej J. Ciesielski and
Emmanuel Boutillon},
title = {Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {33--39},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496664},
doi = {10.1109/HLDVT.2010.5496664},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/Gomez-PradoKCB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/GuglielmoFPSR10,
author = {Giuseppe Di Guglielmo and
Franco Fummi and
Graziano Pravadelli and
Stefano Soffia and
Marco Roveri},
title = {Semi-formal functional verification by {EFSM} traversing via NuSMV},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {58--65},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496660},
doi = {10.1109/HLDVT.2010.5496660},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/GuglielmoFPSR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/LeGD10,
author = {Hoang Minh Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Towards analyzing functional coverage in SystemC {TLM} property checking},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {67--74},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496658},
doi = {10.1109/HLDVT.2010.5496658},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/LeGD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/MahajanM10,
author = {Yogesh S. Mahajan and
Sharad Malik},
title = {Utility of transaction-level hardware models in refinement checking},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {121--128},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496650},
doi = {10.1109/HLDVT.2010.5496650},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hldvt/MahajanM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/Nikhil10,
author = {Rishiyur S. Nikhil},
title = {{ESL} flows are enabled by high-level synthesis with universality},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {137},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496648},
doi = {10.1109/HLDVT.2010.5496648},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/Nikhil10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/SanguinettiZ10,
author = {John Sanguinetti and
Eugene Zhang},
title = {The relationship of code coverage metrics on high-level and {RTL}
code},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {138--141},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496649},
doi = {10.1109/HLDVT.2010.5496649},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/SanguinettiZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/SarbisheiPR10,
author = {Omid Sarbishei and
Yu Pang and
Katarzyna Radecka},
title = {Analysis of range and precision for fixed-point linear arithmetic
circuits with feedbacks},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {25--32},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496667},
doi = {10.1109/HLDVT.2010.5496667},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/SarbisheiPR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/SenA10,
author = {Alper Sen and
Magdy S. Abadir},
title = {Coverage metrics for verification of concurrent SystemC designs using
mutation testing},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {75--81},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496659},
doi = {10.1109/HLDVT.2010.5496659},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/SenA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/VermeulenG10,
author = {Bart Vermeulen and
Kees Goossens},
title = {Obtaining consistent global state dumps to interactively debug systems
on chip with multiple clocks},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496668},
doi = {10.1109/HLDVT.2010.5496668},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/VermeulenG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/YaoZM10,
author = {Haiqiong Yao and
Hao Zheng and
Chris J. Myers},
title = {State space reductions for scalable verification of asynchronous designs},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {17--24},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496666},
doi = {10.1109/HLDVT.2010.5496666},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/YaoZM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hldvt/2010,
title = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://ieeexplore.ieee.org/xpl/conhome/5488975/proceeding},
isbn = {978-1-4244-7805-7},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hldvt/2010.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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