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Publication search results
found 85 matches
- 2000
- Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain:
Expression-tree-based algorithms for code compression on embedded RISC architectures. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 530-533 (2000) - Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos:
Using dynamic cache management techniques to reduce energy in general purpose processors. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 693-708 (2000) - Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George I. Stamoulis:
Architectural and compiler techniques for energy reduction in high-performance microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 317-326 (2000) - Luca Benini, Alessandro Bogliolo, Giovanni De Micheli:
A survey of design techniques for system-level dynamic power management. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 299-316 (2000) - Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Glitch power minimization by selective gate freezing. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 287-298 (2000) - Dinesh Bhatia, James Haralambides:
Resource requirements and layouts for field programmable interconnection chips. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 346-355 (2000) - Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl:
A minimum total power methodology for projecting limits on CMOS GSI. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 235-251 (2000) - Ronald D. Blanton, John P. Hayes:
On the design of fast, easily testable ALU's. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 220-223 (2000) - Alessandro Bogliolo, Michele Favalli, Maurizio Damiani:
Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 415-419 (2000) - Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto:
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 98-103 (2000) - Dominique Borrione, Julia Dushina, Laurence V. Pierre:
A compositional model for the functional verification of high-level synthesis results. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 526-530 (2000) - Fabrice Caignet, S. D.-B. Dhia, Etienne Sicard:
On the measurement of crosstalk in integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 606-609 (2000) - Sek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl:
Heterogeneous architecture models for interconnect-motivated system design. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 660-670 (2000) - Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar:
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 633-636 (2000) - Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Path delay fault simulation of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 223-228 (2000) - Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Improving path delay testability of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 736-741 (2000) - Santanu Chattopadhyay, Shelly Adhikari, Sabyasachi Sengupta, Mahua Pal:
Highly regular, modular, and cascadable design of cellular automata-based pattern classifier. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 724-735 (2000) - Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl:
A compact physical via blockage model. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 689-692 (2000) - Oscal T.-C. Chen, Wei-Lung Liu:
An FIR processor with programmable dynamic data ranges. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 440-446 (2000) - Song Chen, Adam Postula:
Synthesis of custom interleaved memory systems. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 74-83 (2000) - Phillip Christie:
Rent exponent prediction methods. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 679-688 (2000) - Phillip Christie, Dirk Stroobandt:
The interpretation and application of Rent's rule. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 639-648 (2000) - Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen:
System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 129-137 (2000) - Pasquale Corsonello, Stefania Perri, G. Cororullo:
Area-time-power tradeoff in cellular arrays VLSI implementations. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 614-624 (2000) - Sari L. Coumeri, Donald E. Thomas:
Memory modeling for system synthesis. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 327-334 (2000) - Abram P. Dancy, Rajeevan Amirtharajah, Anantha P. Chandrakasan:
High-efficiency multiple-output DC-DC conversion for low-voltage systems. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 252-263 (2000) - Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram:
Improving the efficiency of Monte Carlo power estimation [VLSI]. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 584-593 (2000) - Petru Eles, Alex Doboli, Paul Pop, Zebo Peng:
Scheduling with bus access optimization for distributed embedded systems. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 472-491 (2000) - Farzan Fallah, Stan Y. Liao, Srinivas Devadas:
Solving covering problems using LPR-based lower bounds. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 9-17 (2000) - Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin:
The design of the MGAP-2: a micro-grained massively parallel array. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 709-716 (2000)
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