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Publication search results
found 274 matches
- 2018
- Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu:
A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 933-944 (2018) - Jing Guo, Lei Zhu, Yu Sun, Huiliang Cao, Hai Huang, Tianqi Wang, Chunhua Qi, Rongsheng Zhang, Xuebing Cao, Liyi Xiao, Zhigang Mao:
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 991-994 (2018) - Dong Wang, Pak Kwong Chan:
An Electrical Model for Nanometer CMOS Device Stress Effect in Design and Simulation of Analog Reference Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 958-968 (2018) - Javad Mohebbi Najm Abad, Ali Soleimani:
Novel Feature Selection Algorithm for Thermal Prediction Model. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1831-1844 (2018) - Moataz Abdelfattah, Gordon W. Roberts:
Cascade and LC Ladder-Based Filter Realizations Using Synchronous Time-Mode Signal Processing. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1788-1801 (2018) - Tahmid Abtahi, Colin Shea, Amey M. Kulkarni, Tinoosh Mohsenin:
Accelerating Convolutional Neural Network With FFT on Embedded Hardware. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1737-1749 (2018) - Tosiron Adegbija, Ann Gordon-Ross:
PhLock: A Cache Energy Saving Technique Using Phase-Based Cache Locking. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 110-121 (2018) - Sukarn Agarwal, Hemangee K. Kapoor:
Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1881-1894 (2018) - Pawan Agarwal, Jong-Hoon Kim, Partha Pratim Pande, Deukhyoun Heo:
Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated CMOS Ring PLLs. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 653-662 (2018) - Meysam Akbari, Omid Hashemipour, Farshad Moradi:
Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1812-1816 (2018) - Karim Ali, Fei Li, Sunny Y. H. Lua, Chun-Huat Heng:
Energy- and Area-Efficient Spin-Orbit Torque Nonvolatile Flip-Flop for Power Gating Architecture. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 630-638 (2018) - Muayad J. Aljafar, Marek A. Perkowski, John M. Acken, Robin Tan:
A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND-XOR Structures. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 23-36 (2018) - Md Tanvir Arafin, Gang Qu:
Memristors for Secret Sharing-Based Lightweight Authentication. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2671-2683 (2018) - Mahmood J. Azhar, Fathi Amsaad, Selçuk Köse:
Duty-Cycle-Based Controlled Physical Unclonable Function. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1647-1658 (2018) - Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Farshad Moradi:
Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1051-1058 (2018) - Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty:
Trident: Comprehensive Choke Error Mitigation in NTC Systems. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2195-2204 (2018) - Aatreyi Bal, Shamik Saha, Sanghamitra Roy, Koushik Chakraborty:
Dynamic Choke Sensing for Timing Error Resilience in NTC Systems. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 1-10 (2018) - Arya Balachandran, Yong Chen, Chirn Chye Boon:
A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 599-603 (2018) - Joe Baylon, Xinmin Yu, Srinivasan Gopal, Reza Molavi, Shahriar Mirabbasi, Partha Pratim Pande, Deukhyoun Heo:
A 16-Gb/s Low-Power Inductorless Wideband Gain-Boosted Baseband Amplifier With Skewed Differential Topology for Wireless Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2406-2418 (2018) - Davide Bellizia, Simone Bongiovanni, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti, Francesco Bruno Trotta:
Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1368-1376 (2018) - Imad Benacer, François-Raymond Boyer, Yvon Savaria:
A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1939-1952 (2018) - Ganapati Bhat, Gaurav Singla, Ali K. Unver, Ümit Y. Ogras:
Algorithmic Optimization of Thermal and Power Management for Heterogeneous Mobile Platforms. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 544-557 (2018) - Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya:
Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1026-1039 (2018) - Thierry Bonnoit, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1438-1451 (2018) - Arturo Buscarino, Claudia Corradino, Luigi Fortuna, Leon O. Chua:
Taming Spatiotemporal Chaos in Forced Memristive Arrays. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2947-2954 (2018) - Xin Cai, Mingda Zhou, Tian Xia, Wai H. Fong, Wing-Tsz Lee, Xinming Huang:
Low-Power SDR Design on an FPGA for Intersatellite Communications. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2419-2430 (2018) - Krishnendu Chakrabarty:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2579-2580 (2018) - Supriya Chakraborty, Tinish Bhattacharya, Manan Suri:
Current Optimized Coset Coding for Efficient RRAM Programming. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 1000-1004 (2018) - Wenjie Che, Fareena Saqib, Jim Plusquellic:
Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 733-743 (2018) - Po-Hung Chen, Hao-Chung Cheng, Yi-An Ai, Wang-Ting Chung:
Automatic Mode-Selected Energy Harvesting Interface With >80% Power Efficiency Over 200 nW to 10 mW. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2898-2906 (2018)
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