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Publication search results
found 154 matches
- 2008
- Norbert Abel, Frederik Grüll, Nick Meier, Andreas Beyer, Udo Kebschull:
Parallel hardware objects for dynamically partial reconfiguration. FPL 2008: 563-566 - Panagiotis Afratis, Euripides Sotiriades, Grigorios Chrysos, Sotiria Fytraki, Dionisios N. Pnevmatikatos
:
A rate-based prefiltering approach to blast acceleration. FPL 2008: 631-634 - Mamoun F. Al-Mistarihi:
Separable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGA. FPL 2008: 531-534 - Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner
, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker:
Fine grain reconfigurable architectures. FPL 2008: 348 - Benoît Badrignans, Reouven Elbaz, Lionel Torres:
Secure FPGA configuration architecture preventing system downgrade. FPL 2008: 317-322 - Donald G. Bailey
, Christopher T. Johnston, Ni Ma:
Connected components analysis of streamed images. FPL 2008: 679-682 - Lars Bauer, Muhammad Shafique, Jörg Henkel:
A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor. FPL 2008: 203-208 - Tobias Becker
, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa:
Towards benchmarking energy efficiency of reconfigurable architectures. FPL 2008: 691-694 - Christiane Beuschel, Hans-Jörg Pfleiderer:
FPGA implementation of a flexible decoder for long LDPC codes. FPL 2008: 185-190 - Shilpa Bhoj:
Thermal aware FPGA architectures and CAD. FPL 2008: 701-702 - Shilpa Bhoj, Dinesh Bhatia:
A dynamic temperature control simulation system for FPGAs. FPL 2008: 659-662 - David Boland
, George A. Constantinides:
An FPGA-based implementation of the MINRES algorithm. FPL 2008: 379-384 - Ivo Bolsens:
FPGA: The future platform for transforming, transporting and computing data. FPL 2008: 1 - Oliver Bowen, Christos-Savvas Bouganis
:
Real-time image super resolution using an FPGA. FPL 2008: 89-94 - Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker:
Data path driven waveform-like reconfiguration. FPL 2008: 607-610 - Karel Bruneel, Dirk Stroobandt:
Automatic generation of run-time parameterizable configurations. FPL 2008: 361-366 - Claudio Brunelli, Fabio Garzia, Carmelo Giliberto, Jari Nurmi
:
A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck. FPL 2008: 487-490 - Claudio Brunelli, Fabio Garzia, Jari Nurmi
, Fabio Campi, Damien Picard:
Reconfigurable hardware: The holy grail of matching performance with programming productivity. FPL 2008: 409-414 - Betul Buyukkurt, Walid A. Najjar
:
Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs. FPL 2008: 655-658 - Kevin Camera, Robert W. Brodersen:
An integrated debugging environment for FPGA computing platforms. FPL 2008: 311-316 - Enrique Cantó
, Francesc Fons, Mariano López:
Self-recofigurable embedded systems on Spartan-3. FPL 2008: 571-574 - Ricardo Chaves
, Georgi Kuzmanov, Leonel Sousa
:
On-the-fly attestation of reconfigurable hardware. FPL 2008: 71-76 - Ping Chen, Andy Ye:
The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays. FPL 2008: 427-430 - Gary Chun Tak Chow:
Adaptive precision technique for genetic algorithms. FPL 2008: 705-706 - Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich:
A comparison of embedded reconfigurable video-processing architectures. FPL 2008: 587-590 - Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker:
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. FPL 2008: 535-538 - Immacolata Colacicco, Giacomo Marchiori, Raffaele Tripiccione
:
The hardware application platform of the hartes project. FPL 2008: 439-442 - Eoin Creedon, Michael Manzke
:
Scalable high performance computing on FPGA clusters using message passing. FPL 2008: 443-446 - James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington:
Creating unique identifiers on field programmable gate arrays using natural processing variations. FPL 2008: 579-582 - Jan de Cuveland, Felix Rettig, Venelin Angelov, Volker Lindenstruth:
An FPGA-based high-speed, low-latency trigger processor for high-energy physics. FPL 2008: 293-298
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retrieved on 2024-06-29 22:39 CEST from data curated by the dblp team
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