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Publication search results
found 85 matches
- 2019
- Tjerk Bijlsma
, Marco Jan Gerrit Bekooij, Gerard J. M. Smit:
Circular Buffers with Multiple Overlapping Windows for Cyclic Task Graphs. Trans. High Perform. Embed. Archit. Compil. 5: 39-58 (2019) - Paul M. Carpenter
, Alex Ramírez, Eduard Ayguadé:
The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors. Trans. High Perform. Embed. Archit. Compil. 5: 79-99 (2019) - Ricardo S. Ferreira
, Cristoferson Bueno
, Marcone Laure
, Monica Magalhães Pereira, Luigi Carro
:
A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design. Trans. High Perform. Embed. Archit. Compil. 5: 121-139 (2019) - Andreas Genser, Christian Bachmann, Christian Steger
, Reinhold Weiss, Josef Haid:
A Hardware-Accelerated Estimation-Based Power Profiling Unit - Enabling Early Power-Aware Embedded Software Design and On-Chip Power Management. Trans. High Perform. Embed. Archit. Compil. 5: 59-78 (2019) - George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Xiaojun Yang, Dionisios N. Pnevmatikatos
, Manolis Katevenis:
Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability. Trans. High Perform. Embed. Archit. Compil. 5: 100-120 (2019) - Carlos S. de La Lama
, Pekka Jääskeläinen
, Heikki Kultala
, Jarmo Takala
:
Programmable and Scalable Architecture for Graphics Processing Units. Trans. High Perform. Embed. Archit. Compil. 5: 21-38 (2019) - Richard Membarth
, Hritam Dutta, Frank Hannig
, Jürgen Teich
:
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. Trans. High Perform. Embed. Archit. Compil. 5: 1-20 (2019) - Cristina Silvano, Koen Bertels, Michael J. Schulte:
Transactions on High-Performance Embedded Architectures and Compilers V. Lecture Notes in Computer Science 11225, Springer 2019, ISBN 978-3-662-58833-8 [contents] - 2011
- Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris C. Kirkham, Ian Watson:
Robust Adaptation to Available Parallelism in Transactional Memory Applications. Trans. High Perform. Embed. Archit. Compil. 3: 236-255 (2011) - Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris C. Kirkham, Ian Watson:
Transaction Reordering to Reduce Aborts in Software Transactional Memory. Trans. High Perform. Embed. Archit. Compil. 4: 195-214 (2011) - Arnaldo Azevedo, Ben H. H. Juurlink, Cor Meenderinck, Andrei Sergeevich Terechko
, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez, Mateo Valero:
A Highly Scalable Parallel Implementation of H.264. Trans. High Perform. Embed. Archit. Compil. 4: 111-134 (2011) - Sandro Bartolini, Pierfrancesco Foglia
, Cosimo Antonio Prete:
Eighth MEDEA Workshop. Trans. High Perform. Embed. Archit. Compil. 3: 91-92 (2011) - Valeriu Beiu
, Basheer A. M. Madappuram, Peter M. Kelly, Liam McDaid:
On Two-Layer Brain-Inspired Hierarchical Topologies - A Rent's Rule Approach -. Trans. High Perform. Embed. Archit. Compil. 4: 311-333 (2011) - Matthias A. Blumrich, Valentina Salapura, Alan Gara:
Exploring the Architecture of a Stream Register-Based Snoop Filter. Trans. High Perform. Embed. Archit. Compil. 3: 93-114 (2011) - Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes:
A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors. Trans. High Perform. Embed. Archit. Compil. 4: 63-83 (2011) - Harald Devos, Jan Van Campenhout
, Ingrid Verbauwhede
, Dirk Stroobandt:
Constructing Application-Specific Memory Hierarchies on FPGAs. Trans. High Perform. Embed. Archit. Compil. 3: 201-216 (2011) - Maziar Goudarzi
, Tohru Ishihara
, Hamid Noori
:
Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies. Trans. High Perform. Embed. Archit. Compil. 3: 275-299 (2011) - Michael B. Henry, Leyla Nazhandali:
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture. Trans. High Perform. Embed. Archit. Compil. 4: 175-194 (2011) - Jan Hoogerbrugge, Andrei Sergeevich Terechko
:
A Multithreaded Multicore System for Embedded Media Processing. Trans. High Perform. Embed. Archit. Compil. 3: 154-173 (2011) - Stanley Jaddoe, Mark Thompson, Andy D. Pimentel:
Signature-Based Calibration of Analytical Performance Models for System-Level Design Space Exploration. Trans. High Perform. Embed. Archit. Compil. 4: 409-425 (2011) - Magnus Jahre
, Lasse Natvig:
A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors. Trans. High Perform. Embed. Archit. Compil. 4: 1-20 (2011) - Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella
, Antonio González:
Compiler Directed Issue Queue Energy Reduction. Trans. High Perform. Embed. Archit. Compil. 4: 42-62 (2011) - Omer Khan, Sandip Kundu:
Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors. Trans. High Perform. Embed. Archit. Compil. 4: 84-110 (2011) - Tobias Klug, Michael Ott, Josef Weidendorfer, Carsten Trinitis:
autopin - Automated Optimization of Thread-to-Core Pinning on Multicore Systems. Trans. High Perform. Embed. Archit. Compil. 3: 219-235 (2011) - Isao Kotera, Kenta Abe, Ryusuke Egawa, Hiroyuki Takizawa
, Hiroaki Kobayashi:
Power-Aware Dynamic Cache Partitioning for CMPs. Trans. High Perform. Embed. Archit. Compil. 3: 135-153 (2011) - Fernando Latorre, Grigorios Magklis, José González, Pedro Chaparro, Antonio González
:
CROB: Implementing a Large Instruction Window through Compression. Trans. High Perform. Embed. Archit. Compil. 3: 115-134 (2011) - Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan
:
A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM. Trans. High Perform. Embed. Archit. Compil. 4: 234-253 (2011) - Chun-Chieh Lin, Chuen-Liang Chen:
Cache Sensitive Code Arrangement for Virtual Machine. Trans. High Perform. Embed. Archit. Compil. 3: 24-42 (2011) - Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf:
Advanced Packet Segmentation and Buffering Algorithms in Network Processors. Trans. High Perform. Embed. Archit. Compil. 4: 334-353 (2011) - Miquel Moretó
, Francisco J. Cazorla
, Alex Ramírez, Mateo Valero
:
Dynamic Cache Partitioning Based on the MLP of Cache Misses. Trans. High Perform. Embed. Archit. Compil. 3: 3-23 (2011)
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