- Peter Sandborn, Rajarshi Ghosh, Ken Drake, Magdy S. Abadir, Linda Bal, Ashish Parikh:
Multichip systems trade-off analysis tool. J. Electron. Test. 5(2-3): 207-218 (1994) - Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man:
Design of a C-testable booth multiplier using a realistic fault model. J. Electron. Test. 5(1): 29-41 (1994) - Prab Varma, Tushar Gheewala:
The economics of scan-path design for testability. J. Electron. Test. 5(2-3): 179-193 (1994) - Angus Wu, Jack L. Meador:
Measurement selection for parametric IC fault diagnosis. J. Electron. Test. 5(1): 9-18 (1994) - Farzad Zarrinfar:
Economics of "design for test" to remain competitive in the 90s. J. Electron. Test. 5(2-3): 171-177 (1994) - Thomas A. Ziaja, Earl E. Swartzlander Jr.:
Boundary scan in board manufacturing. J. Electron. Test. 5(2-3): 263-268 (1994)