- Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das:
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers. VLSI Design 2001: 379-384 - Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das:
A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers. VLSI Design 2001: 397-402 - Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
ASIP Design Methodologies : Survey and Issues. VLSI Design 2001: 76- - R. K. Jarwal, Durga Misra:
Degradation Of Nmosfets During High-Field Injection With Reverse Biased Voltage At Source And Drain Junctions. VLSI Design 2001: 485-490 - Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann:
Design Of Provably Correct Storage Arrays. VLSI Design 2001: 196- - Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty:
IBM's Blue Logic Design Methodology-Circuits and Physical Design. VLSI Design 2001: 11-12 - Deepak Kataria:
Next Generation Network Processors. VLSI Design 2001: 13-15 - Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda:
Embedded Memories in System Design: Technology, Application, Design and Tools. VLSI Design 2001: 5-6 - Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal:
Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. VLSI Design 2001: 143-148 - Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri:
Timing Verification and Delay Test Generation for Hierarchical Designs. VLSI Design 2001: 157-162 - Pavan Kumar, Mani B. Srivastava:
Power-aware Multimedia Systems using Run-time Prediction. VLSI Design 2001: 64-69 - Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. VLSI Design 2001: 29-35 - Marcello Lajolo, Matteo Sonza Reorda
, Massimo Violante:
Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. VLSI Design 2001: 371- - Abhijit M. Lele, S. K. Nandy:
Architecture of Reconfigurable a Low Power Gigabit AT Switch. VLSI Design 2001: 242-247 - Mahesh Mehendale, Santhosh Kumar Amanna:
Functional Verification of Programmable DSP Cores. VLSI Design 2001: 16-17 - Noel Menezes, Sachin S. Sapatnekar:
Optimization and Analysis Techniques for the Deep Submicron Regime. VLSI Design 2001: 3-4 - Rex Min, Manish Bhardwaj, Seong-Hwan Cho, Eugene Shih, Amit Sinha, Alice Wang, Anantha P. Chandrakasan:
Low-Power Wireless Sensor Networks. VLSI Design 2001: 205-210 - Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. VLSI Design 2001: 70-75 - Sanjay Mohan, Michael L. Bushnell:
A Code Transition Delay Model for ADC Test. VLSI Design 2001: 274-282 - Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao:
Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. VLSI Design 2001: 479- - Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali:
Average Power in Digital CMOS Circuits using Least Square Estimation. VLSI Design 2001: 215-220 - Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai:
An On-Chip Coupling Capacitance Measurement Technique. VLSI Design 2001: 495-499 - Omkaram Nalamasu, Pat G. Watson, Raymond A. Cirelli, Jeff Bude, Isik C. Kizilyalli, Ross A. Kohler:
Invited Paper: Extending Resolution Limits of IC Fabrication Technology: Demonstration by Device Fabrication and Circuit Performance. VLSI Design 2001: 469 - Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell:
Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. VLSI Design 2001: 365-370 - Dinesh Pamunuwa, Hannu Tenhunen:
Repeater Insertion To Minimise Delay In Coupled Interconnects. VLSI Design 2001: 513-517 - Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan:
Battery Life Estimation of Mobile Embedded Systems. VLSI Design 2001: 57-63 - Siddharth R. Phanse, R. K. Shyamasundar:
Application of Esterel for Modelling and Verification of Cachet Protocol on CRF Memory Model. VLSI Design 2001: 179-188 - Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar:
Accurate Power Macro-modeling Techniques for Complex RTL Circuits. VLSI Design 2001: 235-241 - B. Prasad, P. J. George, Chandra Shekhar:
High Frequency Behaviour Of Electron Transport In Silicon And Its Implication For Drain Conductance Of Mos Transistors. VLSI Design 2001: 491-494 - Anand Raghunathan, Sujit Dey:
Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies. VLSI Design 2001: 9-10
