- Xijiang Lin, Mark Kassab, Janusz Rajski:
Using dynamic shift to reduce test data volume in high-compression designs. ETS 2014: 1-6 - Shudong Lin, Gordon W. Roberts:
Towards a general purpose mixed-signal instrumentation layer in the die stack of a 3D-SIC. ETS 2014: 1-2 - Dmitri Mironov, Raimund Ubar, Jaan Raik:
Logic simulation and fault collapsing with shared structurally synthesized bdds. ETS 2014: 1-2 - Marzieh Mohammadi, Somayeh Sadeghi Kohan, Nasser Masoumi, Zainalabedin Navabi:
An off-line MDSI interconnect BIST incorporated in BS 1149.1. ETS 2014: 1-2 - Madalin Neagu, Liviu Miclea, Salvador Manich:
Interleaved scrambling technique: A novel low-power security layer for cache memories. ETS 2014: 1-2 - Yaara Neumeier, Osnat Keren:
A new efficiency criterion for security oriented error correcting codes. ETS 2014: 1-6 - Eduardo J. Peralías, Antonio Jose Ginés, Adoración Rueda:
INL systematic reduced-test technique for Pipeline ADCs. ETS 2014: 1-6 - Ilia Polian, Jie Jiang, Adit D. Singh:
Detection conditions for errors in self-adaptive better-than-worst-case designs. ETS 2014: 1-6 - Irith Pomeranz:
A distance-based test cube merging procedure for compatible and incompatible test cubes. ETS 2014: 1-2 - Sarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao:
Property-checking based LBIST for improved diagnosability. ETS 2014: 1-2 - Athul Prabhu, Vlado Vorisek, Helmut Lang, Thomas Schumann:
Analysis of cell-aware test pattern effectiveness - A case study using a 32-bit automotive microcontroller. ETS 2014: 1-2 - Walden C. Rhines:
Major eras of Design for Test. ETS 2014: 1 - Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras:
Post-bond test of Through-Silicon Vias with open defects. ETS 2014: 1-6 - Alireza Rohani, Hans G. Kerkhoff:
Two soft-error mitigation techniques for functional units of DSP processors. ETS 2014: 1-6 - Davide Sabena, Luca Sterpone, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus, S. Wong, Robért Glein, Florian Rittner, C. Stender, Mario Porrmann, Jens Hagemeyer:
Reconfigurable high performance architectures: How much are they ready for safety-critical applications? ETS 2014: 1-8 - Thiago Santini, Paolo Rech, Gabriel L. Nazar, Luigi Carro, Flávio Rech Wagner:
Reducing embedded software radiation-induced failures through cache memories. ETS 2014: 1-6 - Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman:
Shadow-scan design with low latency overhead and in-situ slack-time monitoring. ETS 2014: 1-6 - Matthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker:
Variation-aware deterministic ATPG. ETS 2014: 1-6 - Amr A. R. Sayed-Ahmed, Hossam A. H. Fahmy, Ulrich Kühne:
Verification of the decimal floating-point square root operation. ETS 2014: 1-2 - Horst Schirmeier, Lars Rademacher, Olaf Spinczyk:
Smart-hopping: Highly efficient ISA-level fault injection on real hardware. ETS 2014: 1-6 - Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus:
Systematic generation of diagnostic software-based self-test routines for processor components. ETS 2014: 1-6 - Adit D. Singh:
Error detection and recovery in better-than-worst-case timing designs. ETS 2014: 1-6 - Luca Sterpone, Boyang Du:
Analysis and mitigation of single event effects on flash-based FPGAS. ETS 2014: 1-6 - Richard Swanson, Anna Wong, Suraj Ethirajan, Amitava Majumdar:
Avoiding burnt probe tips: Practical solutions for testing internally regulated power supplies. ETS 2014: 1-6 - Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot:
iBoX - Jitter based Power Supply Noise sensor. ETS 2014: 1-2 - Ioannis Voyiatzis:
Accumulator-based test-per-clock scheme for low-power on-chip application of test patterns. ETS 2014: 1-2 - Ioannis Voyiatzis:
Concurrent online BIST for sequential circuits exploiting input reduction and output space compaction. ETS 2014: 1-2 - Marcus Wagner, Hans-Joachim Wunderlich:
Incremental computation of delay fault detection probability for variation-aware test generation. ETS 2014: 1-6 - Giorgio Di Natale:
19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014. IEEE 2014, ISBN 978-1-4799-3415-7 [contents]