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ORCIDHarry Hsieh
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- affiliation: University of California, Riverside, USA
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Journal Articles
- 2009
[j10]Eric Cheung, Xi Chen, Harry Hsieh, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli
, Yosinori Watanabe:
Runtime deadlock analysis for system level design. Des. Autom. Embed. Syst. 13(4): 287-310 (2009)- 2006
- [j9]Xi Chen, Harry Hsieh, Felice Balarin:
Verification Approach of Metropolis Design Framework for Embedded Systems. Int. J. Parallel Program. 34(1): 3-27 (2006) - 2004
- [j8]Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin:
Assertion Based Verification and Analysis of Network Processor Architectures. Des. Autom. Embed. Syst. 9(3): 163-176 (2004) - [j7]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8): 1243-1255 (2004) - 2003
- [j6]Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli:
Metropolis: An Integrated Electronic System Design Environment. Computer 36(4): 45-52 (2003) - [j5]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Formal Verification for Embedded System Designs. Des. Autom. Embed. Syst. 8(2-3): 139-153 (2003) - 2001
- [j4]Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Synchronous approach to the functional equivalence of embeddedsystem implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(8): 1016-1033 (2001) - 1999
- [j3]Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki:
Synthesis of software programs for embedded control applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 834-849 (1999) - 1996
- [j2]Massimiliano Chiodo, Daniel W. Engels, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Kei Suzuki, Alberto L. Sangiovanni-Vincentelli:
A case study in computer-aided co-design of embedded controllers. Des. Autom. Embed. Syst. 1(1-2): 51-67 (1996) - 1994
- [j1]Massimiliano Chiodo, Paolo Giusto, Attila Jurecska, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Luciano Lavagno:
Hardware-software codesign of embedded systems. IEEE Micro 14(4): 26-36 (1994)
Conference and Workshop Papers
- 2009
- [c28]Eric Cheung, Harry Hsieh, Felice Balarin:
Partial order method for timed simulation of system-level MPSoC designs. ASP-DAC 2009: 149-154 - [c27]Eric Cheung, Harry Hsieh, Felice Balarin:
Fast and accurate performance simulation of embedded software for MPSoC. ASP-DAC 2009: 552-557 - [c26]Eric Cheung, Harry Hsieh, Felice Balarin:
Memory subsystem simulation in software TLM/T models. ASP-DAC 2009: 811-816 - 2008
- [c25]Eric Cheung, Harry Hsieh, Felice Balarin:
Software optimization for MPSoC: a mpeg-2 decoder case study. CODES+ISSS 2008: 43-48 - 2007
- [c24]Eric Cheung, Harry Hsieh, Felice Balarin:
Framework for fast and accurate performance simulation of multiprocessor systems. HLDVT 2007: 21-28 - [c23]Eric Cheung, Harry Hsieh, Felice Balarin:
Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip. HLDVT 2007: 37-44 - [c22]Eric Cheung, Xi Chen, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh:
Bridging RTL and gate: correlating different levels of abstraction for design debugging. HLDVT 2007: 73-80 - 2006
- [c21]Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli:
Communication and co-simulation infrastructure for heterogeneous system integration. DATE 2006: 462-467 - [c20]Eric Cheung, Piyush Satapathy, Vi Pham, Harry Hsieh, Xi Chen:
Runtime Deadlock Analysis of SystemC Designs. HLDVT 2006: 187-194 - 2005
- [c19]Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe:
Simulation based deadlock analysis for system level designs. DAC 2005: 260-265 - [c18]Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin:
Assertion-Based Design Exploration of DVS in Network Processor Architectures. DATE 2005: 92-97 - [c17]Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid:
System Synthesis for Networks of Programmable Blocks. DATE 2005: 888-893 - [c16]Susan Cotterell, Ryan Mannion, Frank Vahid, Harry Hsieh:
eBlocks - an enabling technology for basic sensor based systems. IPSN 2005: 422-427 - 2004
- [c15]Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin:
Utilizing Formal Assertions for System Design of Network Processors. DATE 2004: 126-133 - [c14]Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin:
Assertion-based power/performance analysis of network processor architectures. HLDVT 2004: 155-160 - 2003
- [c13]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Case Studies of Model Checking for Embedded System Designs. ACSD 2003: 20-28 - [c12]Susan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh:
First results with eBlocks: embedded systems building blocks. CODES+ISSS 2003: 168-175 - [c11]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Automatic trace analysis for logic of constraints. DAC 2003: 460-465 - [c10]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. DATE 2003: 11174-11175 - [c9]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Verifying LOC based functional and performance constraints. HLDVT 2003: 83-88 - 2002
- [c8]Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Formal verification of embedded system designs at multiple levels of abstraction. HLDVT 2002: 125-130 - 2000
- [c7]Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Efficient methods for embedded system design space exploration. DAC 2000: 607-612 - [c6]Harry Hsieh, Felice Balarin:
Refining abstract equivalence analysis for embedded system design. HLDVT 2000: 139-146 - 1999
- [c5]Harry Hsieh, Felice Balarin:
Synchronous equivalence for embedded systems: a tool for design exploration. ICCAD 1999: 505-510 - 1997
- [c4]Harry Hsieh, Alberto L. Sangiovanni-Vincentelli:
Modeling micro-controller peripherals for high-level co-simulation and synthesis. CODES 1997: 127-130 - 1996
- [c3]Felice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Formal Verification of Embedded Systems based on CFSM Networks. DAC 1996: 568-571 - 1995
- [c2]Massimiliano Chiodo, Paolo Giusto, Attila Jurecska, Luciano Lavagno, Harry Hsieh, Kei Suzuki, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich:
Synthesis of Software Programs for Embedded Control Applications. DAC 1995: 587-592 - 1994
- [c1]Luciano Lavagno, Massimiliano Chiodo, Paolo Giusto, Attila Jurecska, Harry Hsieh, S. Yee, Alberto L. Sangiovanni-Vincentelli, Kei Suzuki:
A case study in computer-aided codesign of embedded controllers. CODES 1994: 220-224
Parts in Books or Collections
- 2003
- [p1]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Simulation Trace Verification for Quantitative Constraints. Embedded Software for SoC 2003: 275-285
Informal and Other Publications
- 2007
- [i2]Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin:
Assertion-Based Design Exploration of DVS in Network Processor Architectures. CoRR abs/0710.4714 (2007) - [i1]Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid:
System Synthesis for Networks of Programmable Blocks. CoRR abs/0710.4798 (2007)
Coauthor Index
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