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ORCIDWilliam B. Toms
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- affiliation: School of Computer Science, University of Manchester, Manchester, UK
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Journal Articles
- 2022
[j6]Eleni Maragkoudaki
, William B. Toms, Vasilis F. Pavlidis:
Energy-Efficient Encoding for High-Speed Serial Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1484-1496 (2022)- 2016
- [j5]Yaman Cakmaki, Will Toms, Javier Navaridas, Mikel Luján:
Cyclic Power-Gating as an Alternative to Voltage and Frequency Scaling. IEEE Comput. Archit. Lett. 15(2): 77-80 (2016) - 2015
- [j4]Behram Khan, Daniel Goodman, Salman Khan, Will Toms, Paolo Faraboschi, Mikel Luján, Ian Watson:
Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems. J. Supercomput. 71(6): 2309-2338 (2015) - 2013
- [j3]P. Balasubramanian, David A. Edwards, William B. Toms:
Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic. J. Circuits Syst. Comput. 22(4) (2013) - 2012
- [j2]P. Balasubramanian, David A. Edwards, William B. Toms:
Redundant Logic Insertion and Latency Reduction in Self-Timed Adders. VLSI Design 2012: 575389:1-575389:13 (2012) - 2011
- [j1]William B. Toms, David A. Edwards:
Indicating combinational logic decomposition. IET Comput. Digit. Tech. 5(4): 331-341 (2011)
Conference and Workshop Papers
- 2023
- [c10]Joshua Lant, Emmanouil Skordalakis, Kyriakos Paraskevas, William B. Toms, Mikel Luján, John Goodacre:
DiAD - Distributed Acceleration for Datacenter FPGAs. FPL 2023: 166-173 - 2021
- [c9]William B. Toms, John Goodacre, Mikel Luján:
Energy Efficient Power-Management for Out-of-Order Processors Using Cyclic Power-Gating. ARCS 2021: 183-198 - 2017
- [c8]John Mawer, Oscar Palomar, Cosmin Gorgovan, Andy Nisbet, Will Toms, Mikel Luján:
The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation. FCCM 2017: 144-151 - 2014
- [c7]Mahdi Jelodari Mamaghani, Jim D. Garside, William B. Toms, Doug A. Edwards:
Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA. DSD 2014: 607-614 - 2010
- [c6]William B. Toms, David A. Edwards:
A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths. ACSD 2010: 24-34 - [c5]William B. Toms, David A. Edwards:
M-of-N Code Decomposition for Indicating Combinational Logic. ASYNC 2010: 15-25 - 2009
- [c4]William B. Toms, Doug A. Edwards:
Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks. ASYNC 2009: 139-150 - 2006
- [c3]William B. Toms, David A. Edwards, Andrew Bardsley:
Synthesising Heterogeneously Encoded Systems. ASYNC 2006: 138-149 - 2005
- [c2]William B. Toms, David A. Edwards:
Efficient synthesis of speed-independent combinational logic circuits. ASP-DAC 2005: 1022-1026 - 2003
- [c1]W. J. Bainbridge, William B. Toms, David A. Edwards, Stephen B. Furber:
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes. ASYNC 2003: 132-140
Coauthor Index
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