"Redundant Logic Insertion and Latency Reduction in Self-Timed Adders."

P. Balasubramanian, David A. Edwards, William B. Toms (2012)

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DOI: 10.1155/2012/575389

access: open

type: Journal Article

metadata version: 2019-06-02

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P. Balasubramanian, David A. Edwards, William B. Toms:
Redundant Logic Insertion and Latency Reduction in Self-Timed Adders. VLSI Design 2012: 575389:1-575389:13 (2012)

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