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ORCIDShang Liu 0006
Person information
- affiliation: Hong Kong University of Science and Technology, Hong Kong, SAR, China
Other persons with the same name
- Shang Liu — disambiguation page
- Shang Liu 0001
![[0000-0002-6576-8243]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-6576-8243")
— China University of Mining and Technology, School of Computer and Science, Xuzhou, China (and 2 more) - Shang Liu 0002 — DAMO Academy Alibaba Group, Beijing, China
- Shang Liu 0003 — Northeastern University, Shenyang, China
- Shang Liu 0004 — Beijing Jiaotong University, Beijing, China
- Shang Liu 0005 — Nanyang Technological University, Singapore
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2020 – today
- 2025
[j2]Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(1): 200-213 (2025)- [j1]Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, Zhiyao Xie:
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(4): 1448-1461 (2025) - [c9]Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. ASP-DAC 2025: 505-512 - [c8]Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie:
Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. ASP-DAC 2025: 527-533 - [c7]Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang:
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. ASP-DAC 2025: 614-621 - [c6]Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie:
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. DAC 2025: 1-7 - [c5]Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie:
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits. DAC 2025: 1-7 - [i7]Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie:
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. CoRR abs/2504.09260 (2025) - [i6]Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie:
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits. CoRR abs/2509.00071 (2025) - 2024
- [c4]Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie:
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. ASPDAC 2024: 722-727 - [c3]Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. DAC 2024: 62:1-62:6 - [c2]Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie:
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation. ICCAD 2024: 60:1-60:9 - [i5]Wenji Fang, Mengming Li, Min Li, Zhiyuan Yan, Shang Liu, Hongce Zhang, Zhiyao Xie:
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR abs/2402.00386 (2024) - [i4]Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. CoRR abs/2403.18453 (2024) - [i3]Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang:
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR abs/2411.14436 (2024) - 2023
- [c1]Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. ICCAD 2023: 1-9 - [i2]Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. CoRR abs/2311.08441 (2023) - [i1]Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie:
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. CoRR abs/2312.08617 (2023)
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