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2020 – today
- 2024
[c15]Guangyu Hu
, Jianheng Tang, Changyuan Yu, Wei Zhang, Hongce Zhang:
DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction. ASPDAC 2024: 262-268- [c14]Zhiyuan Yan, Min Li, Zhengyuan Shi, Wenjie Zhang, Yingcong Chen, Hongce Zhang:
AsymSAT: Accelerating SAT Solving with Asymmetric Graph-Based Model Prediction. DATE 2024: 1-2 - [i7]Wenji Fang, Mengming Li, Min Li, Zhiyuan Yan, Shang Liu, Hongce Zhang, Zhiyao Xie:
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR abs/2402.00386 (2024) - [i6]Chen Chen, Guangyu Hu, Dongsheng Zuo, Cunxi Yu, Yuzhe Ma, Hongce Zhang:
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis. CoRR abs/2403.14242 (2024) - [i5]Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. CoRR abs/2403.18453 (2024) - 2023
- [j2]Wenji Fang, Guangyu Hu, Hongce Zhang:
r-map: Relating Implementation and Specification in Hardware Refinement Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 5113-5126 (2023) - [c13]Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik:
INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms. DAC 2023: 1-4 - [c12]Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. ICCAD 2023: 1-9 - [c11]Guangyu Hu, Wei Zhang, Hongce Zhang:
NeuroPDR: Integrating Neural Networks in the PDR Algorithm for Hardware Model Checking. MLCAD 2023: 1-6 - [c10]Wenji Fang, Hongce Zhang:
WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification. TACAS (2) 2023: 11-18 - [i4]Zhiyuan Yan, Min Li, Zhengyuan Shi, Wenjie Zhang, Yingcong Chen, Hongce Zhang:
Addressing Variable Dependency in GNN-based SAT Solving. CoRR abs/2304.08738 (2023) - [i3]Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. CoRR abs/2311.08441 (2023) - [i2]Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie:
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. CoRR abs/2312.08617 (2023) - 2021
- [c9]Makai Mann, Ahmed Irfan, Florian Lonsing, Yahan Yang, Hongce Zhang, Kristopher Brown, Aarti Gupta, Clark W. Barrett:
Pono: A Flexible and Extensible SMT-Based Model Checker. CAV (2) 2021: 461-474 - [c8]Yu Zeng, Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik:
Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables. ICCAD 2021: 1-9 - [c7]Hongce Zhang, Aarti Gupta, Sharad Malik:
Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking. VMCAI 2021: 325-349 - 2020
- [c6]Hongce Zhang, Maxwell Shinn, Aarti Gupta, Arie Gurfinkel, Nham Le, Nina Narodytska:
Verification of Recurrent Neural Networks for Cognitive Tasks via Reachability Analysis. ECAI 2020: 1690-1697 - [c5]Nina Narodytska, Hongce Zhang, Aarti Gupta, Toby Walsh:
In Search for a SAT-friendly Binarized Neural Network Architecture. ICLR 2020 - [c4]Hongce Zhang, Weikun Yang, Grigory Fedyukovich, Aarti Gupta, Sharad Malik:
Synthesizing Environment Invariants for Modular Hardware Verification. VMCAI 2020: 202-225
2010 – 2019
- 2019
- [j1]Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik:
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. ACM Trans. Design Autom. Electr. Syst. 24(1): 10:1-10:24 (2019) - [c3]Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik:
ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions. TACAS (1) 2019: 351-357 - 2018
- [c2]Hongce Zhang, Caroline Trippel, Yatin A. Manerkar, Aarti Gupta, Margaret Martonosi, Sharad Malik:
ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification. FMCAD 2018: 1-10 - [i1]Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik:
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. CoRR abs/1801.01114 (2018) - 2016
- [c1]Jangseop Shin, Hongce Zhang, Jinyong Lee, Ingoo Heo, Yu-Yuan Chen, Ruby B. Lee, Yunheung Paek:
A hardware-based technique for efficient implicit information flow tracking. ICCAD 2016: 94
Coauthor Index
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