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ORCID"Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing ..."
Wenji Fang et al. (2024)
- Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. CoRR abs/2403.18453 (2024)
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