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ORCIDTsuyoshi Iwagaki
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2020 – today
- 2020
[j7]Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue:
Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(12): 1464-1471 (2020)
2010 – 2019
- 2019
- [j6]Hideyuki Ichihara
, Tatsuyoshi Sugino, Shota Ishii, Tsuyoshi Iwagaki, Tomoo Inoue:
Compact and Accurate Digital Filters Based on Stochastic Computing. IEEE Trans. Emerg. Top. Comput. 7(1): 31-43 (2019) - [c23]Hideyuki Ichihara, Yuki Maeda, Tsuyoshi Iwagaki, Tomoo Inoue:
State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines. DFT 2019: 1-6 - [c22]Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue:
An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis. ITC-Asia 2019: 55-60 - 2017
- [c21]Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue:
State assignment for fault tolerant stochastic computing with linear finite state machines. ITC-Asia 2017: 156-161 - 2015
- [c20]Hideyuki Ichihara, Junpei Kamei, Tsuyoshi Iwagaki, Tomoo Inoue:
A practical approach for logic simplification based on fault acceptability for error tolerant application. ETS 2015: 1-2 - [c19]Tsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue:
Designing area-efficient controllers for multi-cycle transient fault tolerant systems. ETS 2015: 1-2 - [c18]Hideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki, Tomoo Inoue:
Logic simplification by minterm complement for error tolerant application. ICCD 2015: 94-100 - 2014
- [c17]Tsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara, Tomoo Inoue:
Scheduling algorithm in datapath synthesis for long duration transient fault tolerance. DFT 2014: 128-133 - [c16]Hideyuki Ichihara, Shota Ishii, Daiki Sunamori, Tsuyoshi Iwagaki, Tomoo Inoue:
Compact and accurate stochastic circuits with shared random number sources. ICCD 2014: 361-366 - 2013
- [c15]Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue:
A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test. Asian Test Symposium 2013: 85-90 - 2012
- [c14]Tsuyoshi Iwagaki, Takehiro Mikami, Hideyuki Ichihara, Tomoo Inoue:
Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool. APCCAS 2012: 615-618 - [c13]Hideyuki Ichihara, Noboru Shimizu, Tsuyoshi Iwagaki, Tomoo Inoue:
Modeling economics of LSI design and manufacturing for test design selection. ICCD 2012: 516-517 - 2011
- [j5]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(4): 1067-1081 (2011) - [j4]Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko:
Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2563-2570 (2011) - [c12]Tsuyoshi Iwagaki, Kewal K. Saluja:
Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations. DDECS 2011: 175-178 - 2010
- [c11]Tsuyoshi Iwagaki, Mineo Kaneko:
A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties. DELTA 2010: 293-296
2000 – 2009
- 2009
- [j3]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 1096-1105 (2009) - [c10]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Safe clocking for the setup and hold timing constraints in datapath synthesis. ACM Great Lakes Symposium on VLSI 2009: 27-32 - [c9]Tsuyoshi Iwagaki, Mineo Kaneko:
On the derivation of a minimum test set in high quality transition testing. LATW 2009: 1-6 - 2008
- [j2]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 1044-1053 (2008) - [c8]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Safe clocking register assignment in datapath synthesis. ICCD 2008: 120-127 - 2007
- [c7]Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara:
Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD 2007: 418-423 - 2006
- [j1]Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara:
A Low Power Deterministic Test Using Scan Chain Disable Technique. IEICE Trans. Inf. Syst. 89-D(6): 1931-1939 (2006) - [c6]Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation. VLSI-SoC (Selected Papers) 2006: 301-316 - [c5]Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. VLSI-SoC 2006: 308-313 - 2005
- [c4]Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki:
Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. Asian Test Symposium 2005: 444-449 - [c3]Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation. ETS 2005: 48-53 - 2004
- [c2]Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
A design methodology to realize delay testable controllers using state transition information. ETS 2004: 168-173 - 2003
- [c1]Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. Asian Test Symposium 2003: 58-63
Coauthor Index
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