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ORCIDDFT 2014: Amsterdam, The Netherlands
- 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-6155-9
Memories
- Senwen Kan, Jennifer Dworak:
Triggering Trojans in SRAM circuits with X-propagation. 1-8 - Angelo Bacchini, Marco Rovatti, Gianluca Furano, Marco Ottavi:
Characterization of data retention faults in DRAM devices. 9-14 - Chuanlei Zheng, Shuai Wang:
Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors. 15-20
Self Testing
- Martin Omaña, Daniele Rossi
, Edda Beniamino, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche:
Power droop reduction during Launch-On-Shift scan-based logic BIST. 21-26 - Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus:
Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults. 27-32 - Michael A. Skitsas, Chrysostomos Nicopoulos, Maria K. Michael:
Exploration of system availability during software-based self-testing in many-core systems under test latency constraints. 33-39
Security and Fault Tolerance
- Victor Tomashevich, Yaara Neumeier, Raghavan Kumar, Osnat Keren, Ilia Polian:
Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. 40-45 - Md. Tauhidur Rahman, Domenic Forte, Quihang Shi, Gustavo K. Contreras, Mark Mohammad Tehranipoor:
CSST: Preventing distribution of unlicensed and rejected ICs by untrusted foundry and assembly. 46-51 - Jerry Backer, David Hély, Ramesh Karri:
Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip. 52-56 - Prashant D. Joshi, Said Hamdioui:
Security methods in fault tolerant modified line graph based networks. 57-62
Emerging technologies
- Pilin Junsangsri, Jie Han, Fabrizio Lombardi:
A system-level scheme for resistance drift tolerance of a multilevel phase change memory. 63-68 - Wei Wei, Fabrizio Lombardi, Kazuteru Namba:
Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance. 69-74 - Stefano Di Carlo, Marco Indaco, Paolo Prinetto, Elena I. Vatajelu, Rosa Rodríguez-Montañés, Joan Figueras:
Reliability estimation at block-level granularity of spin-transfer-torque MRAMs. 75-80 - Hassen Aziza, Haithem Ayari, Santhosh Onkaraiah, Jean-Michel Portal, Mathieu Moreau, Marc Bocquet:
Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability. 81-85 - Jimson Mathew, Marco Ottavi, Yunfan Yang, Dhiraj K. Pradhan:
Using memristor state change behavior to identify faults in photovoltaic arrays. 86-91
Network on Chip
- Ashkan Eghbal, Pooria M. Yaghini, Siavash S. Yazdi, Nader Bagherzadeh:
TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip. 92-97 - Masoumeh Ebrahimi, Junshi Wang, Letian Huang, Masoud Daneshtalab, Axel Jantsch:
Rescuing healthy cores against disabled routers. 98-103 - Manoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Masoud Daneshtalab, Masoumeh Ebrahimi, Mark Zwolinski:
Fault tolerant and highly adaptive routing for 2D NoCs. 104-109
Sensors
- Jorge Semião, David Saraiva, Carlos Leong, André Romão, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Performance sensor for tolerance and predictive detection of delay-faults. 110-115 - Glenn H. Chapman, Rohit Thomas, Rahul Thomas, Israel Koren, Zahava Koren:
Improved correction for hot pixels in digital imagers. 116-121 - Wisam Aljubouri, Ahish Mysore Somashekar, Themistoklis Haniotakis, Spyros Tragoudas:
Diagnosis of segment delay defects with current sensing. 122-127
Analysis and Synthesis of Resilient Systems
- Tsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara, Tomoo Inoue:
Scheduling algorithm in datapath synthesis for long duration transient fault tolerance. 128-133 - Anup Das, Akash Kumar, Bharadwaj Veeravalli:
Artificial intelligence based task mapping and pipelined scheduling for checkpointing on real time systems with imperfect fault detection. 134-140 - Alirad Malek, Stavros Tzilis, Danish Anis Khan, Ioannis Sourdis, Georgios Smaragdos, Christos Strydis:
A probabilistic analysis of resilient reconfigurable designs. 141-146 - Tiago A. O. Alves, Leandro A. J. Marzulo, Sandip Kundu, Felipe Maia Galvão França:
Domino effect protection on dataflow error detection and recovery. 147-152
Fault Tolerance in FPGA devices
- Lucas A. Tambara, Fernanda Lima Kastensmidt, Paolo Rech, Christopher Frost:
Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAs. 153-158 - Stefano Di Carlo, Paolo Prinetto, Daniele Rolfo, Pascal Trotta:
A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs. 159-164 - Mihalis Psarakis, Alexandros Vavousis, Cristiana Bolchini, Antonio Miele:
Design and implementation of a self-healing processor on SRAM-based FPGAs. 165-170 - Halit Dogan, Domenic Forte, Mark Mohammad Tehranipoor:
Aging analysis for recycled FPGA detection. 171-176 - Jahanzeb Anwer, Marco Platzner:
Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. 177-184
Poster Session I
- Cristian Constantinescu, Srini Krishnamoorthy, Tuyen Nguyen:
Estimating the effect of single-event upsets on microprocessors. 185-190 - Swapnil Bahl, Shreyans Rungta, Shray Khullar, Rohit Kapur, Anshuman Chandra, Salvatore Talluto, Pramod Notiyath, Ajay Rajagopalan:
Unifying scan compression. 191-196 - Florian Haas, Sebastian Weis, Stefan Metzlaff, Theo Ungerer:
Exploiting Intel TSX for fault-tolerant execution in safety-critical systems. 197-202 - Domenico G. Sorrenti, Dario Cozzi, Sebastian Korf, Luca Cassano, Jens Hagemeyer, Mario Porrmann, Cinzia Bernardeschi:
Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems. 203-208 - Daniel A. G. de Oliveira, Paolo Rech, Laércio Lima Pilla, Philippe Olivier Alexandre Navaux, Luigi Carro:
GPGPUs ECC efficiency and efficacy. 209-215 - Stavros Tzilis, Ioannis Sourdis:
A runtime manager for gracefully degrading SoCs. 216-221 - Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, Marvin Onabajo, Yong-Bin Kim:
A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA. 222-227 - Hossein Sayadi, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Seyed Ghassem Miremadi:
A data recomputation approach for reliability improvement of scratchpad memory in embedded systems. 228-233 - Prashant D. Joshi, Said Hamdioui:
Shortest path reduction in a class of uniform fault tolerant networks. 234-239 - Miao Tony He, Mohammad Tehranipoor:
SAM: A comprehensive mechanism for accessing embedded sensors in modern SoCs. 240-245
Poster Session II
- Cristiana Bolchini, Luca Cassano:
Machine learning-based techniques for incremental functional diagnosis: A comparative analysis. 246-251 - Paniz Foroutan, Mehdi Kamal, Zainalabedin Navabi:
A heuristic path selection method for small delay defects test. 252-257 - Thiago Berticelli Lo, Fernanda Lima Kastensmidt, Antonio Carlos Schneider Beck:
Towards an adaptable bit-width NMR voter for multiple error masking. 258-263 - Mohammad Hashem Haghbayan, Bijan Alizadeh, Amir-Mohammad Rahmani, Pasi Liljeberg, Hannu Tenhunen:
Automated formal approach for debugging dividers using dynamic specification. 264-269 - Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Energy-efficient concurrent testing approach for many-core systems in the dark silicon age. 270-275 - In-Seok Jung, Yong-Bin Kim:
A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch. 276-280 - Bartolomeo Montrucchio, Maurizio Rebaudengo, Alejandro Velasco:
Fault injection in the process descriptor of a Unix-based operating system. 281-286 - Bahareh J. Farahani, Saeed Safari:
An instance-based SER analysis in the presence of PVTA variations. 287-292 - Shahrzad Keshavarz, Amirreza Nekooei, Zainalabedin Navabi:
Preemptive multi-bit IJTAG testing with reconfigurable infrastructure. 293-298 - Paolo Bernardi, Riccardo Cantoro, Lyl M. Ciganda Brasca, Ernesto Sánchez, Matteo Sonza Reorda, Sergio de Luca, Renato Meregalli, Alessandro Sansonetti:
On the in-field functional testing of decode units in pipelined RISC processors. 299-304
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