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ORCIDVLSI-SoC 2006: Nice, France - Selected Papers
- Giovanni De Micheli, Salvador Mir, Ricardo Reis:
VLSI-SoC: Research Trends in VLSI and Systems on Chip - Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France. IFIP 249, Springer 2007, ISBN 978-0-387-74908-2 - Sam Kavusi, Kunal Ghosh, Abbas El Gamal:
Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits. 1-23 - Robert K. Henderson, Bruce Rae, David R. Renshaw, Edoardo Charbon:
Oversampled Time Estimation Techniques for Precision Photonic Detectors. 25-35 - Carlotta Guiducci, Claudio Stagni, M. Brocchi, Massimo Lanzoni, Bruno Riccò, Augusto Nascetti
, Davide Caputo, A. De Cesare:
Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices. 37-53 - Ulrich Bockelmann:
Electronic Detection of DNA Adsorption and Hybridization. 55-67 - Shekhar Borkar:
Probabilistic amp; Statistical Design - the Wave of the Future. 69-79 - Shan Jiang, Manh Anh Do, Kiat Seng Yeo:
A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. 81-99 - Lakshmi N. Chakrapani, Jason George, Bo Marr, Bilge Saglam Akgul, Krishna V. Palem:
Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design. 101-118 - Antonis Papanikolaou, Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene:
Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design. 119-141 - Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim:
Soft Error Resilient System Design through Error Correction. 143-156 - Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira:
Library Compatible Variational Delay Computation. 157-176 - Giovanni Beltrame, Donatella Sciuto, Cristina Silvano:
A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures. 177-196 - Jeff Brateman, Changjiu Xian, Yung-Hsiang Lu:
Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots. 197-216 - Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz:
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation. 217-240 - Anna Bernasconi, Valentina Ciriani, Roberto Cordone:
Logic Synthesis of EXOR Projected Sum of Products. 241-257 - Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Reis:
A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits. 259-279 - Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu:
CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization. 281-300 - Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation. 301-316 - Arno Moonen, Chris Bartels, Marco Bekooij, René van den Berg, Harpreet Bhullar, Kees Goossens, Patrick Groeneveld, Jos Huisken, Jef L. van Meerbergen:
Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies. 317-336 - Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo:
Designing Routing and Message-Dependent Deadlock Free Networks on Chips. 337-355 - Ittetsu Taniguchi, Keishi Sakanushi, Kyoko Ueda, Yoshinori Takeuchi, Masaharu Imai:
Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model. 357-376 - Julien Penders, Bert Gyselinckx, Ruud J. M. Vullers, Olivier Rousseaux, Mladen Berekovic, Michael De Nil, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov:
Human++: Emerging Technology for Body Area Networks. 377-397
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