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Journal Articles
- 2023
[j4]Licheng Guo
, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong:
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 16(4): 59:1-59:30 (2023)- 2022
- [j3]Yun Zhou, Pongstorn Maidee, Chris Lavin, Alireza Kaviani, Dirk Stroobandt:
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15(1): 8:1-8:27 (2022) - 2010
- [j2]Pongstorn Maidee, Kia Bazargan:
Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1870-1883 (2010) - 2005
- [j1]Pongstorn Maidee, Cristinel Ababei, Kia Bazargan:
Timing-driven partitioning-based placement for island style FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3): 395-406 (2005)
Conference and Workshop Papers
- 2022
- [c10]Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong:
RapidStream: Parallel Physical Implementation of FPGA HLS Designs. FPGA 2022: 1-12 - 2019
- [c9]Pongstorn Maidee, Chris Neely, Alireza Kaviani, Chris Lavin:
An Open-Source Lightweight Timing Model for RapidWright. FPT 2019: 171-178 - 2017
- [c8]Pongstorn Maidee, Alireza Kaviani, Kevin Zeng:
LinkBlaze: Efficient global data movement for FPGAs. ReConFig 2017: 1-8 - 2015
- [c7]Pongstorn Maidee, Alireza Kaviani:
Improving FPGA NoC performance using virtual cut-through switching technique. ReConFig 2015: 1-6 - 2010
- [c6]Pongstorn Maidee, Kia Bazargan:
A fast SPFD-based rewiring technique. ASP-DAC 2010: 55-60 - 2008
- [c5]Pongstorn Maidee, Nagib Hakim, Kia Bazargan:
FPGA family composition and effects of specialized blocks. FPL 2008: 101-106 - 2007
- [c4]Pongstorn Maidee, Kia Bazargan:
A generalized and unified SPFD-based rewiring technique. FPL 2007: 305-310 - 2006
- [c3]Pongstorn Maidee, Kia Bazargan:
Defect-Tolerant FPGA Architecture Exploration. FPL 2006: 1-6 - 2004
- [c2]Cristinel Ababei, Pongstorn Maidee, Kia Bazargan:
Exploring Potential Benefits of 3D FPGA Integration. FPL 2004: 874-880 - 2003
- [c1]Pongstorn Maidee, Cristinel Ababei, Kia Bazargan:
Fast timing-driven partitioning-based placement for island style FPGAs. DAC 2003: 598-603
Data and Artifacts
- 2021
- [d1]Yun Zhou, Pongstorn Maidee, Chris Lavin, Alireza Kaviani, Dirk Stroobandt:
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs. Zenodo, 2021
Coauthor Index
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