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Chein-Wei Jen
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2000 – 2009
- 2007
- [c47]Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen:
Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. ISCAS 2007: 3506-3509 - 2006
- [c46]Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen:
A 52mW 1200MIPS compact DSP for multi-core media SoC. ASP-DAC 2006: 118-119 - [c45]David Chih-Wei Chang, I-Tao Liao, Jenq Kuen Lee, Wen-Feng Chen, Shau-Yin Tseng, Chein-Wei Jen:
PAC DSP Core and Application Processors. ICME 2006: 289-292 - [c44]Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen:
Programmable FIR filter with adder-based computing engine. ISCAS 2006 - 2005
- [j23]Hun-Chen Chen, Tian-Sheuan Chang
, Jiun-In Guo, Chein-Wei Jen:
The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning. IEICE Trans. Electron. 88-C(5): 1061-1069 (2005) - [j22]Kun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen:
A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding. IEEE Trans. Circuits Syst. Video Technol. 15(2): 283-295 (2005) - [j21]Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang
, Chein-Wei Jen:
A memory-efficient realization of cyclic convolution and its application to discrete cosine transform. IEEE Trans. Circuits Syst. Video Technol. 15(3): 445-453 (2005) - [j20]Kun-Bin Lee, Tzu-Chieh Lin, Chein-Wei Jen:
An Efficient Quality-Aware Memory Controller for Multimedia Platform SoC. IEEE Trans. Circuits Syst. Video Technol. 15(5): 620-633 (2005) - [c43]Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen:
A unified processor architecture for RISC & VLIW DSP. ACM Great Lakes Symposium on VLSI 2005: 50-55 - [c42]Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen:
Architecture for area-efficient 2-D transform in H.264/AVC. ICME 2005: 1126-1129 - [c41]Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen:
Pipelining technique for energy-aware datapaths. ISCAS (2) 2005: 1218-1221 - [c40]Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen:
Hierarchical instruction encoding for VLIW digital signal processors. ISCAS (4) 2005: 3503-3506 - 2004
- [j19]Kun-Bin Lee, Hao-Yun Chin, Nelson Yen-Chung Chang, Hui-Cheng Hsu, Chein-Wei Jen:
Optimal frame memory and data transfer scheme for MPEG-4 shape coding. IEEE Trans. Consumer Electron. 50(1): 342-348 (2004) - [c39]Kun-Bin Lee, Nelson Yen-Chung Chang, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen:
A bandwidth and memory efficient MPEG-4 shape encoder. ASP-DAC 2004: 525-526 - [c38]Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen:
A compact DSP core with static floating-point unit & its microcode generation. ACM Great Lakes Symposium on VLSI 2004: 57-60 - [c37]Nelson Yen-Chung Chang, Kun-Bin Lee, Chein-Wei Jen:
Trace-path analysis and performance estimation for multimedia application in embedded system. ISCAS (2) 2004: 129-132 - [c36]Kun-Bin Lee, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen:
QME: an efficient subsampling-based block matching algorithm for motion estimation. ISCAS (2) 2004: 305-308 - [c35]Kun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen:
A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding. ISCAS (2) 2004: 317-320 - [c34]Kun-Bin Lee, Hui-Cheng Hsu, Chein-Wei Jen:
A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization. ISCAS (2) 2004: 777-780 - [c33]Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen:
Static floating-point unit with implicit exponent tracking for embedded DSP. ISCAS (2) 2004: 821-824 - 2003
- [j18]Wen-Chang Yeh, Chein-Wei Jen:
Generalized Earliest-First Fast Addition Algorithm. IEEE Trans. Computers 52(10): 1233-1242 (2003) - [j17]Wen-Chang Yeh, Chein-Wei Jen:
High-speed and low-power split-radix FFT. IEEE Trans. Signal Process. 51(3): 864-874 (2003) - [j16]Yuan-Chung Lee, Chein-Wei Jen:
Edge-preserving texture filtering for real-time rendering. Vis. Comput. 19(1): 10-22 (2003) - [c32]Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen:
An Efficient VLIW DSP Architecture for Baseband Processing. ICCD 2003: 307-312 - [c31]Tay-Jyi Lin, Chin-Chi Chang, Tsung-Hsun Yang, Yu-Ming Chang, Chien-Hung Lin, Chen-Chia Lee, Hung-Yueh Lin, Chein-Wei Jen:
Performance evaluation of ring-structure register file in multimedia applications. ICME 2003: 121-124 - [c30]Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen:
Coefficient optimization for area-effective multiplier-less FIR filters. ICME 2003: 125-128 - [c29]Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen:
A memory efficient realization of cyclic convolution and its application to discrete cosine transform. ISCAS (4) 2003: 33-36 - [c28]Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen:
Area-effective FIR filter design for multiplier-less implementation. ISCAS (5) 2003: 173-176 - 2002
- [j15]Jen-Chieh Tuan, Tian-Sheuan Chang
, Chein-Wei Jen:
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture. IEEE Trans. Circuits Syst. Video Technol. 12(1): 61-72 (2002) - [j14]Bor-Sung Liang, Yuan-Chung Lee, Wen-Chang Yeh, Chein-Wei Jen:
Index rendering: hardware-efficient architecture for 3-D graphics in multimedia system. IEEE Trans. Multim. 4(3): 343-360 (2002) - [c27]Yun-Tai Hsiao, Hung-Der Lin, Kun-Bin Lee, Chein-Wei Jen:
High-speed memory-saving architecture for the embedded block coding in JPEG2000. ISCAS (5) 2002: 133-136 - [c26]Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen:
A new group distributed arithmetic design for the one dimensional discrete Fourier transform. ISCAS (1) 2002: 421-424 - [c25]Tay-Jyi Lin, Chein-Wei Jen:
CASCADE - configurable and scalable DSP environment. ISCAS (4) 2002: 870-873 - 2001
- [j13]Yuan-Chung Lee, Chein-Wei Jen:
Improved quadratic normal vector interpolation for realistic shading. Vis. Comput. 17(6): 337-352 (2001) - [c24]Yuan-Chung Lee, Chein-Wei Jen:
Arbitrarily scalable edge-preserving interpolation for 3-D graphics and video resizing. ISCAS (2) 2001: 317-320 - [c23]Tay-Jyi Lin, Chein-Wei Jen:
An efficient 2-D DWT architecture via resource cycling. ISCAS (4) 2001: 914-917 - [c22]Ilion Yi-Liang Hsiao, Ding-Hao Wang, Chein-Wei Jen:
Power modeling and low-power design of content addressable memories. ISCAS (4) 2001: 926-929 - 2000
- [j12]Wen-Chang Yeh, Chein-Wei Jen:
High-Speed Booth Encoded Parallel Multiplier Design. IEEE Trans. Computers 49(7): 692-701 (2000) - [j11]Bor-Sung Liang, Chein-Wei Jen:
Computation-effective 3-D graphics rendering architecture for embedded multimedia system. IEEE Trans. Consumer Electron. 46(3): 735-743 (2000) - [j10]Tian-Sheuan Chang
, Chin-Sheng Kung, Chein-Wei Jen:
A simple processor core design for DCT/IDCT. IEEE Trans. Circuits Syst. Video Technol. 10(3): 439-447 (2000) - [c21]Yuan-Chung Lee, Chein-Wei Jen:
On-Line Polygon Refining Using a Low Computation Subdivision Algorithm. GMP 2000: 209-219 - [c20]Wen-Chang Yeh, Chein-Wei Jen:
A high performance carry-save to signed-digit recoder for fused addition-multiplication. ICASSP 2000: 3259-3262 - [c19]Ilion Yi-Liang Hsiao, Chein-Wei Jen:
A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routers. ISCAS 2000: 387-390 - [c18]Bor-Sung Liang, Wen-Chang Yeh, Yuan-Chung Lee, Chein-Wei Jen:
Deferred lighting: a computation-efficient approach for real-time 3-D graphics. ISCAS 2000: 657-660 - [c17]Ching-Long Su, Chein-Wei Jen:
Motion estimation using on-line arithmetic. ISCAS 2000: 683-686
1990 – 1999
- 1999
- [c16]Kun-Bin Lee, Chia-Hsing Lin, Chein-Wei Jen:
Bus buffer modeling and optimization in video processing IP. ICECS 1999: 1779-1782 - 1998
- [c15]Jen-Chien Tuan, Chein-Wei Jen:
An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement. Great Lakes Symposium on VLSI 1998: 152-156 - [c14]Tian-Sheuan Chang, Chein-Wei Jen:
Low power FIR filter realization with differential coefficients and input. ICASSP 1998: 3009-3012 - 1996
- [j9]Jinn-Wang Yeh, Wen-Jiunn Cheng, Chein-Wei Jen:
VASS - A VLSI array system synthesizer. J. VLSI Signal Process. 12(2): 135-158 (1996) - [c13]Chih-Chin Chen, Chein-Wei Jen:
A programmable concurrent video signal processor. ICIP (2) 1996: 1039-1042 - 1995
- [j8]Shifan Chang, Juin-Haur Hwang, Chein-Wei Jen:
Scalable array architecture design for full search block matching. IEEE Trans. Circuits Syst. Video Technol. 5(4): 332-343 (1995) - 1994
- [j7]Shifan Chang, Chein-Wei Jen, Charng Long Lee:
A motion detection scheme for motion adaptive pro-scan conversion. Signal Process. Image Commun. 6(4): 349-356 (1994) - [c12]Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen:
A novel VLSI array design for the discrete Hartley transform using cyclic convolution. ICASSP (2) 1994: 501-504 - [c11]Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen:
A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform. ISCAS 1994: 235-238 - 1993
- [j6]Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen:
A New Array Architecture for Prime-Length Discrete Cosine Transform. IEEE Trans. Signal Process. 41(1): 436-441 (1993) - [j5]Chamg Long Lee, Chein-Wei Jen:
Binary partition algorithms and VLSI architectures for median and rank order filtering. IEEE Trans. Signal Process. 41(9): 2937-2942 (1993) - [c10]Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen:
A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform. ISCAS 1993: 1571-1574 - [c9]Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen:
A Multi-phase Shared Bus Structure for the Fast Fourier Transform. ISCAS 1993: 1575-1578 - [c8]Jiann-Jenn Wang, Chein-Wei Jen:
A High Throughput Systolic Design for QR Algorithm. ISCAS 1993: 1742-1745 - 1992
- [j4]Chein-Wei Jen, Chi-Min Liu:
Design of Two-Level Pipelined Systolic Array and its Application to Image. J. Circuits Syst. Comput. 2(3): 247-264 (1992) - [j3]Chein-Wei Jen, Ding-Ming Kwai:
Data Flow Representation of Iterative Algorithms for Systolic Arrays. IEEE Trans. Computers 41(3): 351-355 (1992) - [j2]Chi-Min Liu, Chein-Wei Jen:
A parallel adaptive algorithm for moving target detection and its VLSI array realization. IEEE Trans. Signal Process. 40(11): 2841-2848 (1992) - [c7]Chien-Piao Lan, Shih-Chieh Wen, Chein-Wei Jen:
Efficient synthesis and high-speed implementation of look-ahead recursive filters. ICASSP 1992: 305-308 - [c6]Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen:
A memory-based approach to design and implement systolic arrays for DFT and DCT. ICASSP 1992: 621-624 - 1991
- [c5]Tung-Hao Huang, Chi-Min Liu, Chein-Wei Jen:
A high-level synthesizer for VLSI array architectures dedicated to digital signal processing. ICASSP 1991: 1221-1224 - 1990
- [c4]Chi-Min Liu, Chein-Wei Jen:
Recursive algorithms for AR spectral estimation and their array realizations. ASAP 1990: 121-132 - [c3]Chi-Min Liu, Bor-Shyong Yang, Chein-Wei Jen:
Parallel adaptive algorithm for moving target indicator and its VLSI array realization. ICASSP 1990: 1795-1798
1980 – 1989
- 1989
- [j1]Chein-Wei Jen, Ding-Ming Kwai:
Multi-dimensional parallel computing structures for regular iterative algorithms. Integr. 8(3): 331-340 (1989) - [c2]Chein-Wei Jen, Chi-Min Liu:
Two-level pipeline design for image resampling. ICASSP 1989: 2441-2444 - 1986
- [c1]Sun-Yuan Kung, Chih-Wei Jim Chang, Chein-Wei Jen:
Real-Time Configuration for Fault-Tolerant VLSI Array Processors. RTSS 1986: 46-54
Coauthor Index
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