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ORCIDSüleyman Sirri Demirsoy
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2020 – today
- 2023
[c17]Norman May, Daniel Ritter, Andre Dossinger, Christian Faerber, Süleyman Sirri Demirsoy:
DASH: Asynchronous Hardware Data Processing Services. CIDR 2023- 2022
- [c16]Robert Lasch, Mehdi Moghaddamfar, Norman May, Süleyman Sirri Demirsoy, Christian Färber, Kai-Uwe Sattler:
Bandwidth-optimal Relational Joins on FPGAs. EDBT 2022: 1:27-1:39 - 2020
- [j2]Robert Lasch
, Ismail Oukid, Roman Dementiev, Norman May, Süleyman Sirri Demirsoy, Kai-Uwe Sattler:
Faster & strong: string dictionary compression using sampling and fast vectorized decompression. VLDB J. 29(6): 1263-1285 (2020) - [c15]Robert Lasch, Süleyman Sirri Demirsoy, Norman May, Veeraraghavan Ramamurthy, Christian Färber, Kai-Uwe Sattler:
Accelerating re-pair compression using FPGAs. DaMoN 2020: 8:1-8:8
2010 – 2019
- 2019
- [c14]Robert Lasch, Ismail Oukid, Roman Dementiev, Norman May, Süleyman Sirri Demirsoy, Kai-Uwe Sattler:
Fast & Strong: The Case of Compressed String Dictionaries on Modern CPUs. DaMoN 2019: 4:1-4:10
2000 – 2009
- 2009
- [c13]Süleyman Sirri Demirsoy, Martin Langhammer:
Cholesky decomposition using fused datapath synthesis. FPGA 2009: 241-244 - [c12]Süleyman Sirri Demirsoy, Kellie Marks:
SoC framework for FPGA: A case study of LTE PUSCH receiver. SoCC 2009: 29-32 - 2008
- [c11]Süleyman Sirri Demirsoy:
Session MA5: Programmable and reconfigurable architectures. ACSCC 2008: 151-152 - 2006
- [c10]Ediz Çetin, Süleyman Sirri Demirsoy, Izzet Kale, Richard C. S. Morling:
A Low-Complexity Self-Calibrating Adaptive Quadrature Receiver. AHS 2006: 428-435 - [c9]Renan Kazazoglu, Süleyman Sirri Demirsoy, Izzet Kale, Richard C. S. Morling:
A computationally efficient DAB bit-stream processor. ISCAS 2006 - 2005
- [c8]Ediz Çetin, Süleyman Sirri Demirsoy, Izzet Kale, Richard C. S. Morling:
Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers. EUSIPCO 2005: 1-4 - [c7]Süleyman Sirri Demirsoy, Izzet Kale, Andrew G. Dempster:
Synthesis of reconfigurable multiplier blocks: part I - fundamentals. ISCAS (1) 2005: 536-539 - [c6]Süleyman Sirri Demirsoy, Izzet Kale, Andrew G. Dempster:
Synthesis of reconfigurable multiplier blocks: part - II algorithm. ISCAS (1) 2005: 540-543 - 2003
- [c5]Süleyman Sirri Demirsoy, Robert Beck, Andrew G. Dempster, Izzet Kale:
Reconfigurable implementation of recursive DCT kernels for reduced quantization noise. ISCAS (4) 2003: 289-292 - [c4]Süleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale:
Design guidelines for reconfigurable multiplier blocks. ISCAS (4) 2003: 293-296 - 2002
- [j1]Süleyman Sirri Demirsoy, Robert Beck, Izzet Kale, Andrew G. Dempster:
New Recursive DCT Implementations with Goertzel filters. Int. J. Comput. 1(1): 45-49 (2002) - [c3]Süleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale:
Power analysis of multiplier blocks. ISCAS (1) 2002: 297-300 - [c2]Andrew G. Dempster, Süleyman Sirri Demirsoy, Izzet Kale:
Designing multiplier blocks with low logic depth. ISCAS (5) 2002: 773-776 - 2000
- [c1]Süleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale:
Transition analysis on FPGA for multiplier-block based FIR filter structures. ICECS 2000: 862-865
Coauthor Index
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