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"A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency ..."

Shinichi Ikeda et al. (2023)

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DOI: 10.1109/A-SSCC58667.2023.10348001

access: closed

type: Conference or Workshop Paper

metadata version: 2024-01-27

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  dblp key:
  - conf/asscc/IkedaIOSISKEMSTSA23
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  - https://dblp.org/rec/conf/asscc/IkedaIOSISKEMSTSA23
Shinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama:
A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems. A-SSCC 2023: 1-3

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