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ORCIDVyacheslav N. Yarmolik
Person information
- affiliation: Belarusian State University, Minsk, Belarus
- affiliation: Bialystok University of Technology, Bialystok, Poland
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Journal Articles
- 2022
[j20]V. N. Yarmolik, Nikolai A. Shevchenko:
Synthesis of Test Sequences with a Given Switching Activity. Autom. Remote. Control. 83(2): 291-302 (2022)- [j19]Ireneusz Mrozek, Nikolai A. Shevchenko, Vyacheslav N. Yarmolik:
Universal Address Sequence Generator for Memory Built-in Self-test. Fundam. Informaticae 188(1): 41-61 (2022) - 2021
- [j18]Ireneusz Mrozek
, Vyacheslav N. Yarmolik:
Transparent Memory Tests Based on the Double Address Sequences. Entropy 23(7): 894 (2021) - 2017
- [j17]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Two-Run RAM March Testing with Address Decimation. J. Circuits Syst. Comput. 26(2): 1750031:1-1750031:17 (2017) - 2016
- [j16]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Multiple Controlled Random Testing. Fundam. Informaticae 144(1): 23-43 (2016) - 2015
- [j15]Vyacheslav N. Yarmolik, Ireneusz Mrozek, Svetlana V. Yarmolik:
Controlled method of random test synthesis. Autom. Control. Comput. Sci. 49(6): 395-403 (2015) - 2014
- [j14]Vyacheslav N. Yarmolik, Svetlana V. Yarmolik:
Address sequences. Autom. Control. Comput. Sci. 48(4): 207-213 (2014) - 2013
- [j13]V. N. Yarmolik, S. V. Yarmolik:
Generating modified Sobol sequences for multiple run march memory tests. Autom. Control. Comput. Sci. 47(5): 242-247 (2013) - 2012
- [j12]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Iterative Antirandom Testing. J. Electron. Test. 28(3): 301-315 (2012) - [j11]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Antirandom Test Vectors for BIST in Hardware/Software Systems. Fundam. Informaticae 119(2): 163-185 (2012) - 2011
- [j10]S. V. Yarmolik, V. N. Yarmolik:
The synthesis of probability tests with a small number of kits. Autom. Control. Comput. Sci. 45(3): 133-141 (2011) - 2010
- [j9]S. V. Yarmolik, Vyacheslav N. Yarmolik:
Generalized adaptive signature analysis. Autom. Control. Comput. Sci. 44(4): 227-233 (2010) - 2009
- [j8]S. V. Yarmolik, V. N. Yarmolik:
Nondestructive RAM testing based on multiple signature comparison. Autom. Control. Comput. Sci. 43(4): 173-178 (2009) - 2008
- [j7]S. V. Yarmolik, Alexander N. Kurbatski, V. N. Yarmolik:
Determination of the optimal initial states for multiple-run RAM testing. Autom. Control. Comput. Sci. 42(3): 120-125 (2008) - [j6]A. A. Ivanyuk, V. N. Yarmolik:
A new approach to the design of built-in internal memory self-testing devices. Autom. Control. Comput. Sci. 42(4): 169-174 (2008) - 2007
- [j5]A. A. Ivanyuk, V. N. Yarmolik:
Injection of functional faults in VHDL-description of digital devices. Autom. Control. Comput. Sci. 41(3): 119-125 (2007) - 2002
- [j4]Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik:
Efficient Online and Offline Testing of Embedded DRAMs. IEEE Trans. Computers 51(7): 801-809 (2002) - 1996
- [j3]Mark G. Karpovsky, Vyacheslav N. Yarmolik:
Transparent random access memory testing for pattern sensitive faults. J. Electron. Test. 9(3): 251-266 (1996) - 1994
- [j2]O. Kebichi, Vyacheslav N. Yarmolik, Michael Nicolaidis:
Zero aliasing ROM BIST. J. Electron. Test. 5(4): 377-388 (1994) - 1983
- [j1]Jan Havel, A. N. Morozevich, Vyacheslav N. Yarmolik:
Generator of randomized pseudorandom numbers. Kybernetika 19(1): 58-65 (1983)
Conference and Workshop Papers
- 2018
- [c23]Eugenia Buslowska, Vyacheslav N. Yarmolik:
Multi-Run March Tests for Pattern Sensitive Faults in RAM. EWDTS 2018: 1-6 - [c22]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Pseudo-Exhaustive Random Access Memory Testing Based on March Tests with Random Background Variation. EWDTS 2018: 1-8 - 2017
- [c21]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Optimal Controlled Random Tests. CISIM 2017: 27-38 - 2016
- [c20]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Methods of Synthesis of Controlled Random Tests. CISIM 2016: 429-440 - 2008
- [c19]Ireneusz Mrozek, Vyacheslav N. Yarmolik, Eugenia Buslowska:
Multi Background Memory Testing. CISIM 2008: 155-156 - [c18]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Optimal Backgrounds Selection for Multi Run Memory Testing. DDECS 2008: 332-338 - 2007
- [c17]Maciej Brzozowski, Vyacheslav N. Yarmolik:
Obfuscation as Intellectual Rights Protection in VHDL Language. CISIM 2007: 337-340 - [c16]Sergei B. Musin, Alexander A. Ivaniuk, Vyacheslav N. Yarmolik:
Multiple Errors Detection Technique for RAM. DDECS 2007: 251-254 - 2006
- [c15]Miroslaw Puczko, V. N. Yarmolik:
Designing cryptographic key generators with low power consumption. DELTA 2006: 418-421 - 1999
- [c14]Sybille Hellebrand, Hans-Joachim Wunderlich, Vyacheslav N. Yarmolik:
Symmetric Transparent BIST for RAMs. DATE 1999: 702-707 - [c13]Vyacheslav N. Yarmolik, I. V. Bykov, Sybille Hellebrand, Hans-Joachim Wunderlich:
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. EDCC 1999: 339-350 - [c12]Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik:
Error Detecting Refreshment for Embedded DRAMs. VTS 1999: 384-390 - 1998
- [c11]Vyacheslav N. Yarmolik, Yuri V. Klimets, Serge N. Demidenko:
March PS(23N) Test for DRAM Pattern-Sensitive Faults. Asian Test Symposium 1998: 354- - [c10]Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich:
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. DATE 1998: 173-179 - [c9]Serge N. Demidenko, Vincenzo Piuri, Vyacheslav N. Yarmolik, A. Shmidman:
BIST Module for Mixed-Signal Circuits. DFT 1998: 349- - 1997
- [c8]Ad J. van de Goor, Georgi Gaydadjiev, Vyacheslav N. Yarmolik, V. G. Mikitjuk:
March LA: a test for linked memory faults. ED&TC 1997: 627 - 1996
- [c7]V. G. Mikitjuk, V. N. Yarmolik, Ad J. van de Goor:
RAM Testing Algorithm for Detection Linked Coupling Faults. ED&TC 1996: 435-441 - [c6]Ad J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik:
March LR: a test for realistic linked faults. VTS 1996: 272-280 - 1995
- [c5]Mark G. Karpovsky, Ad J. van de Goor, V. N. Yarmolik:
Pseudo-exhaustive word-oriented DRAM testing. ED&TC 1995: 126-132 - [c4]O. Kebichi, Michael Nicolaidis, Vyacheslav N. Yarmolik:
Exact Aliasing Computation for RAM BIST. ITC 1995: 13-22 - 1994
- [c3]E. P. Kalosha, Vyacheslav N. Yarmolik, Mark G. Karpovsky:
Signature Testability of PLA. FPL 1994: 335-337 - [c2]Vyacheslav N. Yarmolik, Michael Nicolaidis, O. Kebichi:
Aliasing-free Signature Analysis for RAM BIST. ITC 1994: 368-377 - [c1]Mark G. Karpovsky, Vyacheslav N. Yarmolik:
Transparent Memory Testing for Pattern-Sensitive Faults. ITC 1994: 860-869
Parts in Books or Collections
- 2005
- [p2]Bartosz Sokol, V. N. Yarmolik:
Cryptography and Steganography: teaching experience. Enhanced Methods in Computer Security, Biometric and Artificial Intelligence Systems 2005: 83-92 - [p1]Miroslaw Puczko, V. N. Yarmolik:
Two-pattern test generation with low power consumption based on LFSR. Information Processing and Security Systems 2005: 159-166
Informal and Other Publications
- 2022
- [i1]Ireneusz Mrozek, Nikolai A. Shevchenko, Vyacheslav N. Yarmolik:
Universal Address Sequence Generator for Memory Built-in Self-test. CoRR abs/2208.05325 (2022)
Coauthor Index
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