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Davide Tasca
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Books and Theses
- 2012
- [b1]Davide Tasca:
Low-power low-jitter fractional-N frequency synthesizer using bang bang phase detection. Polytechnic University of Milan, Italy, 2012
Journal Articles
- 2011
- [j4]Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power. IEEE J. Solid State Circuits 46(12): 2745-2758 (2011) - [j3]Davide Tasca, Marco Zanuso, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 200-204 (2011) - 2010
- [j2]Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita:
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic. EURASIP J. Embed. Syst. 2010 (2010) - 2009
- [j1]Marco Zanuso, Davide Tasca, Salvatore Levantino
, Andrea Donadel, Carlo Samori
, Andrea L. Lacaita
:
Noise Analysis and Minimization in Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. II Express Briefs 56-II(11): 835-839 (2009)
Conference and Workshop Papers
- 2011
- [c3]Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power. ISSCC 2011: 88-90 - 2009
- [c2]Marco Zanuso, Salvatore Levantino
, Davide Tasca, Daniele Raiteri, Carlo Samori
, Andrea L. Lacaita
:
A glitch-corrector circuit for low-spur ADPLLs. ICECS 2009: 595-598 - [c1]Salvatore Levantino
, Marco Zanuso, Davide Tasca, Carlo Samori
, Andrea L. Lacaita
:
An all-digital architecture for low-jitter regulated delay lines. ICECS 2009: 603-606
Coauthor Index
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