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Journal Articles
- 2006
[j3]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
:
A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. 22(1): 89-99 (2006)- 2004
- [j2]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Power-Driven Routing-Constrained Scan Chain Design. J. Electron. Test. 20(6): 647-660 (2004) - 2000
- [j1]Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos:
Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. 16(3): 193-202 (2000)
Conference and Workshop Papers
- 2004
- [c14]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains. DATE 2004: 62-67 - [c13]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains. DELTA 2004: 287-294 - 2003
- [c12]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC 2003: 488-493 - 2002
- [c11]Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur:
Integrating DFT in the Physical Synthesis Flow. ITC 2002: 788-795 - 2001
- [c10]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium 2001: 253-258 - [c9]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW 2001: 87-89 - [c8]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS 2001: 306-311 - 2000
- [c7]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium 2000: 459-464 - [c6]Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch:
Low power BIST design by hypergraph partitioning: methodology and architectures. ITC 2000: 652-661 - 1999
- [c5]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium 1999: 89-94 - [c4]Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos:
Low power BIST by filtering non-detecting vectors. ETW 1999: 165-170 - [c3]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI 1999: 24- - [c2]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos:
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) 1999: 110-113 - [c1]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS 1999: 407-412
Coauthor Index
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