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2020 – today
- 2023
[j3]Seungjong Lee
, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn:
An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer. IEEE J. Solid State Circuits 58(4): 929-938 (2023)- [j2]Kyumin Kwon, Omar A. B. Abdelatty, David D. Wentzloff:
PLL Fractional Spur's Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter. IEEE J. Solid State Circuits 58(5): 1271-1284 (2023) - [c4]Kyumin Kwon, David D. Wentzloff:
Synthesizable ADPLL Generator: From Specification to GDS. SMACD 2023: 1-4 - 2022
- [j1]Hyochan An, Samuel R. Nason-Tomaszewski, Jongyup Lim, Kyumin Kwon, Matthew S. Willsey, Parag G. Patil, Hun-Seok Kim, Dennis Sylvester, Cynthia A. Chestek, David T. Blaauw:
A Power-Efficient Brain-Machine Interface System With a Sub-mw Feature Extraction and Decoding ASIC Demonstrated in Nonhuman Primates. IEEE Trans. Biomed. Circuits Syst. 16(3): 395-408 (2022) - [c3]Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn:
An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer. VLSI Technology and Circuits 2022: 54-55 - 2020
- [c2]Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff:
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. VLSI-SoC (Selected Papers) 2020: 65-85 - [c1]Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff:
An Open-source Framework for Autonomous SoC Design with Analog Block Generation. VLSI-SOC 2020: 141-146
Coauthor Index
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