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Cheng-Hsun Lu
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2020 – today
- 2024
- [j2]Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Rani Kale, Mark Flanigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang:
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. IEEE J. Solid State Circuits 59(4): 1235-1245 (2024) - [j1]Jie-Fang Zhang, Cheng-Hsun Lu, Zhengya Zhang:
TetriX: Flexible Architecture and Optimal Mapping for Tensorized Neural Network Processing. IEEE Trans. Computers 73(5): 1219-1232 (2024) - [c3]Cheng-Hsun Lu, Wei Tang, Jiyoon Han, Zhengya Zhang:
An 11.4mm2 40.2Gbps 17.4pJ/b/Iteration Soft-Decision Open Forward Error Correction Decoder for Optical Communications. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c2]Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang:
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. VLSI Technology and Circuits 2023: 1-2
2010 – 2019
- 2019
- [c1]Cheng-Hsun Lu, Yi-Chung Wu, Chia-Hsiang Yang:
A 2.25 TOPS/W Fully-Integrated Deep CNN Learning Processor with On-Chip Training. A-SSCC 2019: 65-68
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last updated on 2024-10-18 20:33 CEST by the dblp team
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