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"Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm ..."

Wei Tang et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185388

access: closed

type: Conference or Workshop Paper

metadata version: 2023-07-30

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  - https://dblp.org/rec/conf/vlsit/TangCHBZCLZTWMY23
Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang:
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm² AIB 2.0 Interface to Provide Versatile Workload Acceleration. VLSI Technology and Circuits 2023: 1-2

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