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Monalisa Das

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2020 – today

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2022
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Monalisa Das, Babita Jajodia:
Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGA. ISOCC 2022: 65-66
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Monalisa Das, Babita Jajodia:
FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware Primitives. ISOCC 2022: 81-82

2010 – 2019

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2019
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Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya:
Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1231-1244 (2019)
2017
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Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya:
A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. iNIS 2017: 210-214

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