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ORCIDYusuke Kanno
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2020 – today
- 2024
[c4]Sakiko Itoh
, Tomomi Sakano, Mieko Sagawa, Rie Yanagiya, Yusuke Kanno, Kayo Hirooka, Sakiko Fukui:
Home Care Services in the Last Year of Life by Type of Care Management. Nursing Informatics 2024: 685-686- 2020
- [j6]Yusuke Kanno, Tadanobu Toba, Kotaro Shimamura, Nobuyasu Kanekawa:
Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 726-735 (2020)
2010 – 2019
- 2017
- [j5]Makoto Saen, Tadanobu Toba, Yusuke Kanno:
Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA. IEICE Trans. Electron. 100-C(4): 382-390 (2017) - 2014
- [j4]Goichi Ono, Yuki Mori, Michiaki Nakayama, Yusuke Kanno:
A Method for Measuring of RTN by Boosting Word-Line Voltage in 6-Tr-SRAMs. IEICE Trans. Electron. 97-C(3): 215-221 (2014) - 2012
- [c3]Kosuke Ino, Mustafa Sen, Taku Nishijo, Yusuke Kanno, Hitoshi Shiku, Tomokazu Matsue:
Comprehensive electrochemical imaging with local redox cycling-based electrochemical chip device for evaluation of three-dimensional culture cells. MHS 2012: 16-18 - 2010
- [j3]Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, Koichiro Ishibashi:
A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS. IEEE J. Solid State Circuits 45(11): 2312-2320 (2010)
2000 – 2009
- 2007
- [j2]Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie:
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. IEEE J. Solid State Circuits 42(1): 74-83 (2007) - [j1]Yusuke Kanno, Yuki Kondoh, Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu, Shigenobu Komatsu, Hiroyuki Mizuno:
In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution. IEEE J. Solid State Circuits 42(4): 784-789 (2007) - 2006
- [c2]Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
Hierarchical power distribution and power management scheme for a single chip mobile processor. DAC 2006: 292-295 - [c1]Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie:
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. ISSCC 2006: 2200-2209
Coauthor Index
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