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ORCIDChittaranjan Mandal 0002
Person information
- affiliation: Indian Institute of Technology, Department of Computer Science and Engineering, Kharagpur, India
Other persons with the same name
- Chittaranjan A. Mandal (aka: Chittaranjan Mandal 0001, Chitta Mandal) — ERNET, India
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Journal Articles
- 2023
[j16]Chandrani Ray Chowdhury
, Sudip Misra, Chittaranjan Mandal:
Energy-Aware Service Allocation: A Crow Search-Based Approach. IEEE Trans. Green Commun. Netw. 7(1): 211-223 (2023)- [j15]Chandrani Ray Chowdhury, Sudip Misra, Chittaranjan Mandal, Samaresh Bera:
SeamFlow: Seamless Flow Forwarding in Energy Harvesting-Enabled Access Points of SDWLAN. IEEE Trans. Sustain. Comput. 8(1): 94-108 (2023) - 2022
- [j14]Chandrani Ray Chowdhury, Sudip Misra, Chittaranjan Mandal:
IEEE 802.11k-Based Lightweight, Distributed, and Cooperative Access Point Coverage Estimation Scheme in IoT Networks. IEEE Internet Things J. 9(12): 10139-10148 (2022) - [j13]Ilora Maity, Sudip Misra, Chittaranjan Mandal:
SCOPE: Cost-Efficient QoS-Aware Switch and Controller Placement in Hybrid SDN. IEEE Syst. J. 16(3): 4873-4880 (2022) - [j12]Devleena Ghosh, Chittaranjan Mandal:
Clustering Based Parameter Estimation of Thyroid Hormone Pathway. IEEE ACM Trans. Comput. Biol. Bioinform. 19(1): 343-354 (2022) - [j11]Chandrani Ray Chowdhury, Chittaranjan Mandal, Sudip Misra:
Sustainable Maintenance of Connected Dominating Set by Solar Energy Harvesting for IoT Networks. IEEE Trans. Green Commun. Netw. 6(4): 2115-2127 (2022) - [j10]Ilora Maity, Sudip Misra, Chittaranjan Mandal:
ETHoS: Energy-Aware Traffic Engineering for Sustainable Hybrid SDN. IEEE Trans. Sustain. Comput. 7(4): 875-886 (2022) - 2021
- [j9]Ilora Maity, Sudip Misra, Chittaranjan Mandal:
DART: Data Plane Load Reduction for Traffic Flow Migration in SDN. IEEE Trans. Commun. 69(3): 1765-1774 (2021) - [j8]Ilora Maity, Sudip Misra, Chittaranjan Mandal:
CORE: Prediction-Based Control Plane Load Reduction in Software-Defined IoT Networks. IEEE Trans. Commun. 69(3): 1835-1844 (2021) - [j7]Arindam Das, Manoj Kumar Gangwar, Devleena Ghosh, Chittaranjan Mandal, Anirban Sengupta, M. Mubashshir Waris:
Automatic Generation of Route Control Chart From Validated Signal Interlocking Plan. IEEE Trans. Intell. Transp. Syst. 22(10): 6516-6525 (2021) - 2020
- [j6]Saheb Halder, Subhajit Samaddar, Karunamoy Purkait, Abhoy Mondal, Chittaranjan R. Mandal, Malay Purkait:
Double electron capture in fast ion-atom collisions. J. Comput. Methods Sci. Eng. 20(2): 665-686 (2020) - [j5]Partha De, Udaya Parampalli, Chittaranjan Mandal:
Secure Path Balanced BDD-Based Pre-Charge Logic for Masking. IEEE Trans. Circuits Syst. 67-I(12): 4747-4760 (2020) - 2019
- [j4]Ilora Maity, Ayan Mondal, Sudip Misra, Chittaranjan Mandal:
Tensor-Based Rule-Space Management System in SDN. IEEE Syst. J. 13(4): 3921-3928 (2019) - [j3]Partha De, Chittaranjan Mandal, Udaya Parampalli:
Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1080-1092 (2019) - 2018
- [j2]Ilora Maity, Ayan Mondal, Sudip Misra, Chittaranjan Mandal:
CURE: Consistent Update With Redundancy Reduction in SDN. IEEE Trans. Commun. 66(9): 3974-3981 (2018) - 2017
- [j1]Bibhas Ghoshal, Chittaranjan Mandal, Indranil Sengupta:
Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs. Integr. 59: 168-178 (2017)
Conference and Workshop Papers
- 2020
- [c6]Ilora Maity, Sudip Misra, Chittaranjan Mandal:
Traffic-Aware Consistent Flow Migration in SDN. ICC 2020: 1-6 - 2015
- [c5]Devleena Ghosh, Chittaranjan Mandal:
Layout Validation Using Graph Grammar and Generation of Yard Specific Safety Properties for Railway Interlocking Verification. APSEC 2015: 330-337 - [c4]Gargi Roy, Devleena Ghosh, Chittaranjan Mandal:
A Virtual Laboratory Package to Support Teaching of Logic Design and Computer Organization. T4E 2015: 3-6 - [c3]Gargi Roy, Devleena Ghosh, Chittaranjan Mandal, Indraneel Mitra:
Aiding Teaching of Logic Design and Computer Organization through Dynamic Problem Generation and Automatic Checker Using COLDVL Tool. T4E 2015: 15-22 - 2013
- [c2]Bibhas Ghoshal, Chittaranjan Mandal, Indranil Sengupta:
Re-using Refresh for Self-Testing DRAMs. ISED 2013: 118-122 - 2006
- [c1]Palanichamy Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, Chittaranjan R. Mandal:
Asynchronous Design Methodology for an Efficient Implementation of Low power ALU. APCCAS 2006: 590-593
Coauthor Index
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