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ORCIDRakesh H. Patel
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2000 – 2009
- 2009
[c11]Albert Vareljian, Mohsen Moussavi, William Bereza, Walter Fergusson, Charles E. Berndt, Rakesh H. Patel:
Nonlinear behavior study in digital bang-bang PLL. CICC 2009: 339-342- 2008
- [c10]Rakesh H. Patel, Michael Seningen:
Session 21 - Leveraging the third Dimension. CICC 2008 - 2007
- [c9]Walter Fergusson, Rakesh H. Patel, William Bereza:
Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A. CICC 2007: 857-860 - 2006
- [c8]Rakesh H. Patel, William Bereza:
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs. CICC 2006: 97-100 - [c7]William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel:
PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. DAC 2006: 1013-1016 - 2005
- [c6]Shoujun Wang, Haitao Mei, Mashkoor Baig, William Bereza, Tadeusz Kwasniewski, Rakesh H. Patel:
Design considerations for 2nd-order and 3rd-order bang-bang CDR loops. CICC 2005: 317-320 - [c5]Yuming Tao, William Bereza, Rakesh H. Patel, Sergey Y. Shumarayev, Tad A. Kwasniewski:
A signal integrity-based link performance simulation platform. CICC 2005: 725-728 - [c4]Rakesh H. Patel, Paul Billig:
Nanometer design intricacies. CICC 2005: 758-759 - [c3]Ramanand Venkata, Vinson Chan, Binh Ton, Chong Lee, Huy Ngo, Malik Kabani, Tam Nguyen, Arch Zaliznyak, Ning Xue, Steven Shen, Michael Zheng, Michael Lai, Steve Park, Lana Chan, Divya Vijayaraghavan, John Lam, Rakesh H. Patel:
Multi-protocol embedded PCS IP in a FPGA-SOC. CICC 2005: 783-786 - 2004
- [c2]Henry Y. Lui, Chong H. Lee, Rakesh H. Patel:
Power estimation and thermal budgeting methodology for FPGAs. CICC 2004: 711-714 - 2002
- [c1]Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev:
Interconnect enhancements for a high-speed PLD architecture. FPGA 2002: 3-10
Coauthor Index
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