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"Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs."

Rakesh H. Patel, William Bereza (2006)

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DOI: 10.1109/CICC.2006.320979

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Rakesh H. Patel, William Bereza:
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs. CICC 2006: 97-100

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