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ORCIDIvan Siu-Chuang Lu
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2020 – today
- 2022
[j4]Venumadhav Bhagavatula
, Fan Zhang, Che-Chun Kuo, Anirban Sarkar, Ashutosh Verma, Tienyu Chang, Xiaohua Yu, Daeyoung Yoon, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho:
A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control. IEEE J. Solid State Circuits 57(5): 1257-1266 (2022)- [c5]Ashutosh Verma, Venumadhav Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang-Ivan Lu, Sang Won Son, Thomas Byunghak Cho:
A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW. ISSCC 2022: 1-3
2010 – 2019
- 2019
- [j3]Wanghua Wu, Chih-Wei Yao, Kunal Godbole, Ronghua Ni, Pei-Yuan Chiang, Yongping Han, Yongrong Zuo, Ashutosh Verma, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho:
A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction. IEEE J. Solid State Circuits 54(5): 1254-1265 (2019) - 2017
- [c4]Venumadhav Bhagavatula, Dae Hyun Kwon, Jaehun Lee, Quang-Diep Bui, Jeong-Hyun Choi, Siuchuang-Ivan Lu, Sang Won Son:
13.3 A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOS. ISSCC 2017: 220-221 - 2011
- [j2]Chi-Yao Yu, Ivan Siu-Chuang Lu, Yen-Horng Chen, Lan-chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, Hsiang-Hui Chang, Wen-Chang Lee, Sheng-Jui Huang, Tzung-Han Wu, Chinq-Shiun Chiu, George Chien:
A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC. IEEE J. Solid State Circuits 46(12): 3047-3060 (2011) - [c3]Ivan Siu-Chuang Lu, Chi-Yao Yu, Yen-Horng Chen, Lan-chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, George Chien:
A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC. ISSCC 2011: 364-366
2000 – 2009
- 2007
- [j1]Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran:
A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider. IEEE Trans. Circuits Syst. II Express Briefs 54-II(4): 323-327 (2007) - 2006
- [c2]Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran:
ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective. VLSI Design 2006: 575-580 - 2005
- [c1]Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran:
The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4 GHz band. WCNC 2005: 776-781
Coauthor Index
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