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Hiren D. Patel

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Anirudh M. Kaushik

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Publications

2023
[j24]
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  - journals/tecs/KlashtornyWKP23
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Artem Klashtorny, Zhuanhao Wu, Anirudh Mohan Kaushik, Hiren D. Patel:
Predictable GPU Wavefront Splitting for Safety-Critical Systems. ACM Trans. Embed. Comput. Syst. 22(5s): 107:1-107:25 (2023)
[c59]
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  - conf/rtas/WuKP23
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Zhuanhao Wu, Anirudh M. Kaushik, Hiren D. Patel:
ZeroCost-LLC: Shared LLCs at No Cost to WCL. RTAS 2023: 249-261
2022
[j22]
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  - journals/tcad/KaushikP22
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Anirudh Mohan Kaushik, Hiren D. Patel:
Automatic Construction of Predictable and High-Performance Cache Coherence Protocols for Multicore Real-Time Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3318-3331 (2022)
2021
[j21]
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  - journals/taco/KaushikPP21
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Anirudh Mohan Kaushik, Gennady Pekhimenko, Hiren D. Patel:
Gretch: A Hardware Prefetcher for Graph Analytics. ACM Trans. Archit. Code Optim. 18(2): 18:1-18:25 (2021)
[j19]
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Anirudh Mohan Kaushik, Mohamed Hassan, Hiren D. Patel:
Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems. IEEE Trans. Computers 70(12): 2098-2111 (2021)
[c53]
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Anirudh Mohan Kaushik, Hiren D. Patel:
Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols. DATE 2021: 816-821
[c52]
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  - conf/rtas/WuKTP21
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Zhuanhao Wu, Anirudh Mohan Kaushik, Paulos Tegegn, Hiren D. Patel:
A Hardware Platform for Exploring Predictable Cache Coherence Protocols for Real-time Multicores. RTAS 2021: 92-104
[c51]
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Anirudh Mohan Kaushik, Hiren D. Patel:
A Systematic Approach to Achieving Tight Worst-Case Latency and High-Performance Under Predictable Cache Coherence. RTAS 2021: 105-117
2019
[c48]
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  - conf/rtss/KaushikTWP19
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Anirudh M. Kaushik, Paulos Tegegn, Zhuanhao Wu, Hiren D. Patel:
CARP: A Data Communication Mechanism for Multi-core Mixed-Criticality Systems. RTSS 2019: 419-432
[c47]
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  - conf/rtss/SritharanKHP19
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Nivedita Sritharan, Anirudh M. Kaushik, Mohamed Hassan, Hiren D. Patel:
Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems. RTSS 2019: 433-445
2018
[j16]
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  - journals/tecs/HassanKP18
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Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel:
Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis. ACM Trans. Embed. Comput. Syst. 17(5): 90:1-90:25 (2018)
2017
[c45]
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Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel:
Predictable Cache Coherence for Multi-core Real-Time Systems. RTAS 2017: 235-246
[i1]
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  - journals/corr/SritharanKHP17
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Nivedita Sritharan, Anirudh M. Kaushik, Mohamed Hassan, Hiren D. Patel:
HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems. CoRR abs/1706.07568 (2017)
2015
[c40]
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Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel:
Reverse-engineering embedded memory controllers through latency-based analysis. RTAS 2015: 297-306
2013
[c35]
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  - conf/date/BertaccoCBFVKP13
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Valeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, Anirudh M. Kaushik, Hiren D. Patel:
On the use of GP-GPUs for accelerating compute-intensive EDA applications. DATE 2013: 1357-1366
[c34]
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  - conf/fdl/KaushikP13
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Anirudh M. Kaushik, Hiren D. Patel:
Systemc-clang: An open-source framework for analyzing mixed-abstraction SystemC models. FDL 2013: 1-8
2012
[c28]
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  - conf/hldvt/NanjundappaKPS12
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Mahesh Nanjundappa, Anirudh M. Kaushik, Hiren D. Patel, Sandeep K. Shukla:
Accelerating SystemC simulations using GPUs. HLDVT 2012: 132-139

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