Chun-Po Huang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Jai-Ming Lin

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Publications

2016
[j5]
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Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang:
An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1730-1743 (2016)
[j3]
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  - journals/tvlsi/HuangLSC16
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Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, Soon-Jyh Chang:
A Systematic Design Methodology of Asynchronous SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1835-1848 (2016)
2013
[j2]
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  - journals/tvlsi/ShyuLHLLC13
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Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang:
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 624-635 (2013)
2012
[j1]
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  - journals/tcad/LinLCHC12
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Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang:
Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1789-1802 (2012)
2011
[c2]
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  - conf/dac/LinLCHC11
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Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang:
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits. DAC 2011: 528-533
2010
[c1]
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  - conf/dac/LinLHC10
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Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang:
Performance-driven analog placement considering boundary constraint. DAC 2010: 292-297

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